Geoffrey B. Stephens

Person

Catlett, VA, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS device and circuit and method of operation dynamically control...
- Patent number 6,275,094
- Issue date Aug 14, 2001
- International Business Machines Corporation
- Hayden Clavie Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage CMOS circuit for on/off chip drive at high voltage
- Patent number 6,031,394
- Issue date Feb 29, 2000
- International Business Machines Corporation
- Hayden C. Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for testing quiescent current in integrated ci...
- Patent number 5,939,897
- Issue date Aug 17, 1999
- International Business Machines Corporation
- Robert Lee Ayers
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing quiescent current in integrated ci...
- Patent number 5,760,598
- Issue date Jun 2, 1998
- International Business Machines Corporation
- Robert Lee Ayers
- G01 - MEASURING TESTING
Information Patent Grant
Reduced power VLSI chip and driver circuit
- Patent number 5,453,705
- Issue date Sep 26, 1995
- International Business Machines Corporation
- Francois I. Atallah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mixed voltage output buffer circuit
- Patent number 5,424,659
- Issue date Jun 13, 1995
- International Business Machines Corp.
- Geoffrey B. Stephens
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual electron injection structure and process with self-limiting ox...
- Patent number 4,656,729
- Issue date Apr 14, 1987
- International Business Machines Corp.
- Charles T. Kroll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On chip charge trap compensated high voltage converter
- Patent number 4,481,566
- Issue date Nov 6, 1984
- International Business Machines Corporation
- Charles R. Hoffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for fabricating semi-conductive oxide between two poly sili...
- Patent number 4,458,407
- Issue date Jul 10, 1984
- International Business Machines Corporation
- Anthony J. Hoeg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage on chip FET driver
- Patent number 4,429,237
- Issue date Jan 31, 1984
- International Business Machines Corp.
- Hayden C. Cranford
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fabrication method for vertical PNP structure with Schottky barrier...
- Patent number 4,412,376
- Issue date Nov 1, 1983
- IBM Corporation
- David E. De Bar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically alterable read only memory cell
- Patent number 4,404,577
- Issue date Sep 13, 1983
- International Business Machines Corp.
- Hayden C. Cranford
- G11 - INFORMATION STORAGE
Information Patent Grant
Forming an integrated circuit
- Patent number 4,395,812
- Issue date Aug 2, 1983
- IBM Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky Barrier diode with controlled characteristics
- Patent number 4,373,166
- Issue date Feb 8, 1983
- IBM Corporation
- D. L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky barrier diode with controlled characteristics and fabricat...
- Patent number 4,357,178
- Issue date Nov 2, 1982
- IBM Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and process for optimizing the characteristics of I.sup.2...
- Patent number 4,326,212
- Issue date Apr 20, 1982
- IBM Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense high performance JFET compatible with NPN transistor formatio...
- Patent number 4,314,267
- Issue date Feb 2, 1982
- IBM Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense dry etched multi-level metallurgy with non-overlapped vias
- Patent number 4,289,834
- Issue date Sep 15, 1981
- IBM Corporation
- George E. Alcorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage compensation of temperature coefficient of resistance in an...
- Patent number 4,229,753
- Issue date Oct 21, 1980
- International Business Machines Corporation
- David L. Bergeron
- G05 - CONTROLLING REGULATING
Information Patent Grant
Hardened photoresist master image mask process
- Patent number 4,201,800
- Issue date May 6, 1980
- International Business Machines Corp.
- George E. Alcorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dense dry etched multi-level metallurgy with non...
- Patent number 4,172,004
- Issue date Oct 23, 1979
- International Business Machines Corporation
- George E. Alcorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized oxidation enhancement for an integrated injection logic c...
- Patent number 4,157,268
- Issue date Jun 5, 1979
- International Business Machines Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NPN/PNP Fabrication process with improved alignment
- Patent number 4,110,126
- Issue date Aug 29, 1978
- International Business Machines Corporation
- David L. Bergeron
- H01 - BASIC ELECTRIC ELEMENTS

Geoffrey B. Stephens

Person

Patents Grantslast 30 patents

CMOS device and circuit and method of operation dynamically control...

Low voltage CMOS circuit for on/off chip drive at high voltage

Method and apparatus for testing quiescent current in integrated ci...

Method and apparatus for testing quiescent current in integrated ci...

Reduced power VLSI chip and driver circuit

Mixed voltage output buffer circuit

Dual electron injection structure and process with self-limiting ox...

On chip charge trap compensated high voltage converter

Process for fabricating semi-conductive oxide between two poly sili...

High voltage on chip FET driver

Fabrication method for vertical PNP structure with Schottky barrier...

Electrically alterable read only memory cell

Forming an integrated circuit

Schottky Barrier diode with controlled characteristics

Schottky barrier diode with controlled characteristics and fabricat...

Structure and process for optimizing the characteristics of I.sup.2...

Dense high performance JFET compatible with NPN transistor formatio...

Dense dry etched multi-level metallurgy with non-overlapped vias

Voltage compensation of temperature coefficient of resistance in an...

Hardened photoresist master image mask process

Method for forming dense dry etched multi-level metallurgy with non...

Localized oxidation enhancement for an integrated injection logic c...

NPN/PNP Fabrication process with improved alignment