Gerald S. Pasdast

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock-gating in die-to-die (D2D) interconnects
- Patent number 12,362,306
- Issue date Jul 15, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite interposer structure and method of providing same
- Patent number 12,362,284
- Issue date Jul 15, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compliance and debug testing of a die-to-die interconnect
- Patent number 12,353,305
- Issue date Jul 8, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-to-die interconnect
- Patent number 12,332,826
- Issue date Jun 17, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sideband interface for die-to-die interconnects
- Patent number 12,321,305
- Issue date Jun 3, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PHY-based retry techniques for die-to-die interfaces
- Patent number 12,316,343
- Issue date May 27, 2025
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Skip level vias in metallization layers for integrated circuit devices
- Patent number 12,315,794
- Issue date May 27, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic voltage regulator sensing for chiplet-based designs
- Patent number 12,306,216
- Issue date May 20, 2025
- Intel Corporation
- Vikrant Thigle
- G01 - MEASURING TESTING
Information Patent Grant
Skip level vias in metallization layers for integrated circuit devices
- Patent number 12,288,746
- Issue date Apr 29, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitors and resistors at direct bonding interfaces in microelect...
- Patent number 12,266,682
- Issue date Apr 1, 2025
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual loop voltage regulator
- Patent number 12,164,319
- Issue date Dec 10, 2024
- Intel Corporation
- Sathya Narasimman Tiagaraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable and interoperable PHYLESS die-to-die IO solution
- Patent number 12,159,840
- Issue date Dec 3, 2024
- Intel Corporation
- Zhiguo Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Approximate data bus inversion technique for latency sensitive appl...
- Patent number 12,117,960
- Issue date Oct 15, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microelectronic assemblies with inductors in direct bonding regions
- Patent number 12,107,060
- Issue date Oct 1, 2024
- Intel Corproation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power-forwarding bridge for inter-chip data signal transfer
- Patent number 12,100,662
- Issue date Sep 24, 2024
- Intel Corporation
- Zhiguo Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies with inductors in direct bonding regions
- Patent number 12,062,631
- Issue date Aug 13, 2024
- Intel Corporation
- Adel A Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite interposer structure and method of providing same
- Patent number 12,014,990
- Issue date Jun 18, 2024
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,899,615
- Issue date Feb 13, 2024
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite IC chips including a chiplet embedded within metallizatio...
- Patent number 11,749,649
- Issue date Sep 5, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vias in composite IC chip structures
- Patent number 11,694,986
- Issue date Jul 4, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite interposer structure and method of providing same
- Patent number 11,652,059
- Issue date May 16, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,586,579
- Issue date Feb 21, 2023
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer-deserializer die for high speed signal interconnect
- Patent number 11,581,282
- Issue date Feb 14, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package or structure with dual-sided interposers and...
- Patent number 11,367,707
- Issue date Jun 21, 2022
- Intel Corporation
- Shawna M. Liff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fast-lane routing for multi-chip packages
- Patent number 11,336,559
- Issue date May 17, 2022
- Intel Corporation
- Adel A. Elsherbini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,294,852
- Issue date Apr 5, 2022
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite interposer structure and method of providing same
- Patent number 11,270,947
- Issue date Mar 8, 2022
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vias in composite IC chip structures
- Patent number 11,205,630
- Issue date Dec 21, 2021
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite IC chips including a chiplet embedded within metallizatio...
- Patent number 11,094,672
- Issue date Aug 17, 2021
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip package link
- Patent number 11,003,610
- Issue date May 11, 2021
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIDIRECTIONAL LINK WITH HYBRID SUPPRESSION CIRCUIT
- Publication number 20250112660
- Publication date Apr 3, 2025
- Intel Corporation
- Horaira ABU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS
- Publication number 20240355768
- Publication date Oct 24, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME
- Publication number 20240274542
- Publication date Aug 15, 2024
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC VOLTAGE REGULATOR SENSING FOR CHIPLET-BASED DESIGNS
- Publication number 20240183884
- Publication date Jun 6, 2024
- Intel Corporation
- Vikrant Thigle
- G01 - MEASURING TESTING
Information Patent Application
PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS
- Publication number 20240063132
- Publication date Feb 22, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...
- Publication number 20240030172
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME
- Publication number 20230245972
- Publication date Aug 3, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORWARDED SUPPLY VOLTAGE FOR DYNAMIC VOLTAGE AND FREQUENCY SCALING...
- Publication number 20230245999
- Publication date Aug 3, 2023
- Intel Corporation
- Gerald S. Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SER...
- Publication number 20230197676
- Publication date Jun 22, 2023
- Intel Corporation
- Gerald S. Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY
- Publication number 20230197677
- Publication date Jun 22, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARCHITECTURE WITH INTEGRATED CIRCUIT DIES OVER INPUT/OUTP...
- Publication number 20230197675
- Publication date Jun 22, 2023
- Intel Corporation
- Gerald S. Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE
- Publication number 20230187407
- Publication date Jun 15, 2023
- Intel Corporation
- Carleton L. Molnar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20230169032
- Publication date Jun 1, 2023
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER DELIVERY THROUGH CAPACITOR-DIES IN A MULTI-LAYERED MICROELECT...
- Publication number 20230163098
- Publication date May 25, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20230130935
- Publication date Apr 27, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS
- Publication number 20230100228
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPAIR AND PERFORMANCE CHIPLET
- Publication number 20230100375
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE
- Publication number 20230095914
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES
- Publication number 20220399277
- Publication date Dec 15, 2022
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES
- Publication number 20220399324
- Publication date Dec 15, 2022
- Intel Corporation
- Han Wui Then
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING
- Publication number 20220393672
- Publication date Dec 8, 2022
- Jayen Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING

Gerald S. Pasdast

Person

Patents Grantslast 30 patents

Clock-gating in die-to-die (D2D) interconnects

Composite interposer structure and method of providing same

Compliance and debug testing of a die-to-die interconnect

Die-to-die interconnect

Sideband interface for die-to-die interconnects

PHY-based retry techniques for die-to-die interfaces

Skip level vias in metallization layers for integrated circuit devices

Dynamic voltage regulator sensing for chiplet-based designs

Skip level vias in metallization layers for integrated circuit devices

Capacitors and resistors at direct bonding interfaces in microelect...

Dual loop voltage regulator

Scalable and interoperable PHYLESS die-to-die IO solution

Approximate data bus inversion technique for latency sensitive appl...

Microelectronic assemblies with inductors in direct bonding regions

Power-forwarding bridge for inter-chip data signal transfer

Microelectronic assemblies with inductors in direct bonding regions

Composite interposer structure and method of providing same

Multiple dies hardware processors and methods

Composite IC chips including a chiplet embedded within metallizatio...

Vias in composite IC chip structures

Composite interposer structure and method of providing same

Multiple dies hardware processors and methods

Serializer-deserializer die for high speed signal interconnect

Semiconductor package or structure with dual-sided interposers and...

Fast-lane routing for multi-chip packages

Multiple dies hardware processors and methods

Composite interposer structure and method of providing same

Vias in composite IC chip structures

Composite IC chips including a chiplet embedded within metallizatio...

Multichip package link

Patents Applicationslast 30 patents

BIDIRECTIONAL LINK WITH HYBRID SUPPRESSION CIRCUIT

MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME

DYNAMIC VOLTAGE REGULATOR SENSING FOR CHIPLET-BASED DESIGNS

PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS

THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME

FORWARDED SUPPLY VOLTAGE FOR DYNAMIC VOLTAGE AND FREQUENCY SCALING...

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SER...

PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY

PACKAGING ARCHITECTURE WITH INTEGRATED CIRCUIT DIES OVER INPUT/OUTP...

FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

POWER DELIVERY THROUGH CAPACITOR-DIES IN A MULTI-LAYERED MICROELECT...

SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES

PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS

REPAIR AND PERFORMANCE CHIPLET

TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE

SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES

ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES

CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS