TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.

Description

TECHNICAL FIELD

Embodiments of the present disclosure relate to electronic packages, and more particularly to electronic packages with test and/or debug chiplets that are attached with a hybrid bonding interconnect (HBI) architecture.

BACKGROUND

There is a practical limitation to the number of view ports in a microchip. There is also a practical limitation to the number of signals/nodes that can be effectively routed to each of the mentioned view IO ports. This leads the microchip designers to limit the number of nodes within the microchip that can be viewed directly by testing equipment. Often, these limitations make post silicon testing and debugging more difficult and take a relatively long time. As such, there can be delays in time to market upon the arrival of the first silicon. In some instances test engineers rely on focused ion beam (FIB) to generate probe points within the die that do not have view pins/visibility muxed out in the design. However, such FIB processes are time consuming and expensive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustration of a die with a plurality of functional blocks, in accordance with an embodiment.

FIG. 1B is a plan view illustration of a die with a plurality of functional blocks and an array of hybrid bonding interconnect (HBI) pads over a surface of the die, in accordance with an embodiment.

FIG. 1C is a plan view illustration of a die with HBI pads over one of the functional blocks of the die, in accordance with an embodiment.

FIG. 1D is a plan view illustration of a die with uniform HBI pads over each of the functional blocks of the die, in accordance with an embodiment.

FIG. 2 is a cross-sectional illustration of a test chiplet, in accordance with an embodiment.

FIG. 3 is a cross-sectional illustration of the HBI interface between a test chiplet and a die, in accordance with an embodiment.

FIG. 4A is a cross-sectional illustration of a die with a test chiplet attached, in accordance with an embodiment.

FIG. 4B is a cross-sectional illustration of a die with the test chiplet removed, in accordance with an embodiment.

FIG. 5A is a cross-sectional illustration of a die with a test chiplet attached to a backside surface of the die, in accordance with an embodiment.

FIG. 5B is a cross-sectional illustration of a die with a test chiplet attached to a backside surface of the die, where additional HBI pads are left unconnected, in accordance with an embodiment.

FIG. 6A is a cross-sectional illustration of an electronic system with a die that includes a test chiplet, in accordance with an embodiment.

FIG. 6B is a cross-sectional illustration of an electronic system with a test chiplet on the backside of the electronic system.

FIG. 7 is a schematic of a computing device built in accordance with an embodiment.

EMBODIMENTS OF THE PRESENT DISCLOSURE

Described herein are electronic packages with test and/or debug chiplets that are attached with a hybrid bonding interconnect (HBI) architecture, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, there is a practical limit to the number of view ports in a microchip. Accordingly, test and debug processes can be extremely challenging. In some instances focused ion beam (FIB) processes are needed to generate pads to regions that are not serviced by existing DFx hooks. Accordingly, embodiments disclosed herein include the use of hybrid bonding interconnect (HBI) architectures in order to generate the DFx hooks on the die. The use of HBI architectures is particularly beneficial because the pads have a much smaller size and pitch. As such, there is support for a significantly higher number of nodes within the die without having to rout/mux all of them to a view pin or pins. One can simply add an HBI pad to all desired nodes. In post silicon testing, special assemblies can be fabricated with probe chiplets (connected by HBI, so as to allow inclusion with minimal resource allocation) to provide views for desired nodes. The HBI architecture allows for more DFx hooks to be provided on the die. The DFx hooks can be coupled to a test chiplet using the HBI architectures. In some embodiments, the test chiplets are kept on the die, and in other embodiments, the test chiplets are removed from the die before sale to the customer.

Referring now to FIG. 1A, a plan view illustration of a die 100 is shown, in accordance with an embodiment. In an embodiment, the die 100 may comprise a substrate 105. The substrate 105 may be a silicon substrate or any other semiconductor substrate. The substrate 105 may comprise a plurality of functional blocks 110. As shown, the functional blocks 110 may have different dimensions and orientations across the surface of the substrate 105. In an embodiment, the functional blocks 110 may comprise any functional block typical of a die. For example, the functional blocks 110 may comprise a processor core, a memory block, IO blocks, and the like. In a particular embodiment, the die 100 may be considered a system on a chip (SOC). Though, it is to be appreciated that other types of dies 100 may be used in accordance with embodiments disclosed herein.

Referring now to FIG. 1B, a plan view illustration of a die 100 is shown, in accordance with an additional embodiment. In an embodiment, the die 100 may be substantially similar to the die 100 described above with respect to FIG. 1A. For example, the die 100 may comprise a substrate 105 and functional blocks 110. Additionally, the die 100 may comprise an array of HBI pads 115. Each of the HBI pads 115 may be coupled to a node within the die 100. In other embodiments, multiple nodes may be muxed to a single HBI pad 115.

The HBI pads 115 may be formed in a regular array across a surface of the die 100. In an embodiment, the HBI pads 115 are formed over the backside surface of the die 100. That is, the HBI pads 115 are opposite from the first level interconnects (FLIs) (not shown in FIG. 1B). However, in other embodiments, HBI pads 115 may also be formed on the FLI side of the die 100, as will be described in greater detail below.

In an embodiment, the HBI pads 115 have a pitch and size that allows for more HBI pads 115 than what is possible with existing DFx hooks. While shown as a 13×19 array in FIG. 1B, it is to be appreciated that thousands or tens of thousands of the HBI pads 115 may be provided across the die 100. For example, the HBI pads 115 may have a pitch P that is approximately 20 μm or less, or approximately 10 μm or less. As used herein, “approximately” refers to a range of values within 10% of the stated value. For example, “approximately 10 μm” may refer to a range that is between 9 μm and 11 μm.

In the illustrated embodiment, the HBI pads 115 have a regular array with columns and rows. The array of the HBI pads 115 may include HBI pads 115 that are not directly over one of the functional blocks 110. For example, HBI pads 115 may be over an edge of an underlying functional block 110 or entirely outside of footprints of underlying functional blocks 110.

Referring now to FIG. 1C, a plan view illustration of a die 100 is shown, in accordance with an embodiment. In an embodiment, the die 100 may be substantially similar to the die 100 in FIG. 1A. That is, the die 100 may comprise a substrate 105 and a plurality of functional blocks 110. In an embodiment, an array of HBI pads 115 may be formed over the die 100. In an embodiment, the HBI pads 115 may be formed over a backside of the die 100 opposite from the FLI side. In other embodiments, the HBI pads 115 may be provided over the FLI side, as will be described in greater detail below.

In contrast to the embodiment shown in FIG. 1B, the array of HBI pads 115 includes separate sub-arrays over each of the functional blocks 110. That is, each sub-array of the HBI pads 115 are provided over one of the functional blocks 110. That way, test chiplets (described in greater detail below) may be coupled to the functional block 110 that is being investigated. In an embodiment, the HBI pads 115 for each functional block 110 may be substantially similar. That is, the pitch and size of the HBI pads 115 may be the same for each functional block 110. In other embodiments, the HBI pads 115 may have different sizes and/or pitches depending on which functional block 110 the HBI pad 115 is servicing.

Referring now to FIG. 1D, a cross-sectional illustration of a die 100 is shown, in accordance with an additional embodiment. In an embodiment, the die 100 may comprise a substrate 105 with a plurality of functional blocks 110. The die 100 may be substantially similar to the die 100 described above with respect to FIG. 1A.

In an embodiment, the die 100 may have a plurality of HBI arrays 116. Each HBI array 116 may be provided over one of the functional blocks 110. That is, the nodes from the underlying functional block 110 may be routed to the HBI pads 115 in the HBI array 116. While shown as a four by four array, it is to be appreciated that the HBI arrays 116 may comprise hundreds or thousands of HBI pads 115.

In an embodiment, the plurality of HBI arrays 116 may all be substantially similar to each other. As such, a single test chiplet may be used to test each of the functional blocks 110. In other embodiments, the HBI arrays 116 may be non-uniform across the die 100. For example, larger functional blocks 110 may include larger HBI arrays 116 in order to provide DFx hooks to more nodes.

Referring now to FIG. 2, a cross-sectional illustration of a test chiplet 220 is shown, in accordance with an embodiment. In an embodiment, the test chiplet 220 may be coupled to a die (not shown) in order to provide testing of one or more functional blocks on the die. In an embodiment, the test chiplet 220 comprises a substrate 222. The substrate 222 may be a silicon substrate or other semiconductor substrate. In an embodiment, through substrate vias (TSVs) 223 pass through a thickness of the substrate 222. In an embodiment, the TSVs 223 end at a backside pad 228. The backside pad 228 may be covered by a solder ball 227. The solder ball 227 may be used to connect the test chiplet 220 to an external device for testing.

In an embodiment, the opposite side of the test chiplet 220 may be the HBI interface. The HBI interface may comprise a plurality of HBI pads 225. The HBI pads 225 may be copper or other conductive material. In an embodiment, the HBI pads 225 are surrounded by a dielectric layer 226. In an embodiment, the dielectric layer 226 may comprise any suitable dielectric material for HBI architectures, such as a dielectric comprising silicon and oxygen (e.g., SiOx). The bottom surface of the dielectric layer 226 and the bottom surface of the HBI pads 225 may be substantially coplanar with each other. In some embodiments, “substantially coplanar” may refer to two surfaces being within approximately 1 μm of being coplanar. In other embodiments, the HBI pads 225 may be recessed from the dielectric layer 226. The recess may be approximately 100 nm or less, or approximately 10 nm or less.

In an embodiment, the HBI pads 225 may be coupled to the TSVs 223 through a routing layer 221. The routing layer 221 may be a passive layer (i.e., with no active transistor circuitry). In other embodiments, the routing layer 221 may be an active layer (i.e., with active transistor circuitry). For example, the routing layer 221 may include circuitry for muxing or otherwise combining multiple HBI pads 225 into a single lane. In an embodiment, the routing layer 221 may also provide circuitry for supporting the testing of the underlying die. For example, the routing layer 221 may include standard testing interfaces used in die testing and debugging.

Referring now to FIG. 3, a cross-sectional illustration of a device with a die substrate 305 coupled to a test chiplet 320 is shown, in accordance with an embodiment. In an embodiment, the die substrate 305 may be a silicon substrate or other semiconductor material. Functional blocks (not shown in FIG. 3) may be incorporated into the die substrate 305. The die substrate 305 may be similar to any of the dies 100 described in greater detail above. In an embodiment, the test chiplet 320 may also comprise a silicon or other semiconductor substrate. The test chiplet 320 may be substantially similar to the test chiplet 220 described with respect to FIG. 2.

In an embodiment, the test chiplet 320 is coupled to the die substrate 305 with an HBI architecture. On the test chiplet 320 side, first pads 325 and a first dielectric layer 326 are provided. In an embodiment, the first pads 325 may comprise copper or any other suitable conductive material, and the first dielectric layer 326 may comprise any suitable dielectric material, such as one comprising silicon and oxygen (e.g., SiOx). On the die substrate 305, second pads 315 and a second dielectric layer 317 are provided. In an embodiment, the second pads 315 may comprise copper or any other suitable conductive material, and the second dielectric layer 317 may comprise any suitable dielectric material, such as one comprising silicon and oxygen (e.g., SiOx).

In an embodiment, the bonding of the test chiplet 320 to the die substrate 305 may be a two part operation. First, at a low temperature, the first dielectric layer 326 bonds to the second dielectric layer 317. Then, at a higher temperature, the first pads 325 bond to the second pads 315. The first pads 325 and the second pads 315 may be bonded together by diffusion bonding processes. In some instances, the diffusion between the bond of the first pads 325 and the second pads 315 may result in there being no discernable interface. As such, it may appear as though there is a single conductive feature between the test chiplet 320 and the die substrate 305.

In an embodiment, the HBI architecture allows for the conductive pads 315 and 325 to have relatively small pitches. For example, a pitch P between conductive pads 325 and 315 may be approximately 20 μm or smaller, or approximately 10 μm or smaller. In some embodiments, the pitch P may be approximately 1 μm or smaller. That is, the pitch P may be at the nanometer scale. Such small pitches allow for the number of DFx hooks to be orders of magnitude more than existing testing architectures. As such, testing and debugging is simplified since more nodes can be viewed without the need for FIB technologies.

Referring now to FIG. 4A, a cross-sectional illustration of a die module 440 is shown, in accordance with an embodiment. In an embodiment, the die module 440 comprises a die substrate 405. The die substrate 405 may be a silicon substrate or another suitable semiconductor material. In an embodiment, the die substrate 405 may be substantially similar to the die substrates 105 described in greater detail above. In an embodiment, routing layers 441 may be provided over a surface of the die substrate 405. As shown, HBI pads 415 may be provided at the surface of the routing layers 441. Some of the HBI pads 415 may be routed to FLIs 444 by vias 443 through a resist layer 442. In other instances, the HBI pads 415 may be coupled to a test chiplet 420.

In an embodiment, the test chiplet 420 may be similar to the test chiplet 220 described in greater detail above. For example, the test chiplet 420 may be an active or passive device. In an embodiment, the test chiplet 420 may comprise HBI pads 425. The HBI pads 425 may be bonded to the HBI pads 415 of the die substrate 405. In an embodiment, the surrounding dielectric layer 426 may also be bonded to the dielectric layer over the routing layers 441 on the die side. In an embodiment, the HBI pads 415 may be electrically coupled to TSVs 423 that pass through the test chiplet 422. The TSVs 423 may be coupled to FLIs 444.

In an embodiment, the test chiplet 420 may persist as part of the final structure of the die module 440. That is, in the device that is ultimately sold to a customer, the test chiplet 420 may be included. Including the test chiplet 420 may be useful for testing units that are returned in order to find out why a device stopped working or otherwise malfunctioned.

However, in other embodiments, the test chiplet 420 may not be present in the final structure of the die module 440. For example, as shown in FIG. 4B, a cavity 445 is provided where the test chiplet was positioned. Such an embodiment may occur when the test chiplet 420 is used for debugging and testing purposes, but is not needed during production of the die modules 440. While shown as having a cavity 445, it is to be appreciated that the layer 442 may be continuous across the routing layers 441 and cover the unutilized HBI pads 415. It is to be appreciated that the presence of the HBI pads 415 may be used to indicate that a test chiplet 420 architecture was used. For example, the HBI pads 415 may persist into the units sold to customers. Such units would include HBI pads 415 that seemingly do not connect to any external FLIs 444, or other external connections. That is, during operation of the die 405, some of the HBI pads 415 may be non-functional pads and be electrically floating.

Referring now to FIG. 5A, a cross-sectional illustration of a die module 550 is shown, in accordance with an embodiment. In an embodiment, the die module 550 comprises a die substrate 505. The die substrate 505 may be a semiconductor substrate, such as a silicon substrate. The die substrate 505 may also comprise a plurality of functional blocks (not shown). For example, the die substrate 505 may be an SOC or the like. In an embodiment, the die module 550 may further comprise a test chiplet 520. The test chiplet 520 may be an active or passive device used to test or debug nodes within the die substrate 505. The test chiplet 520 may be substantially similar to the test chiplet 220 described with respect to FIG. 2.

In an embodiment, the test chiplet 520 is provided on a backside surface of the die substrate 505. That is, the test chiplet 520 is provided on a surface of the die substrate 505 that is opposite from the FLIs 544. This is different than the embodiment described with respect to FIG. 4A, where the test chiplet 420 is provided on the FLI side of the die substrate 405. In the illustrated embodiment, the test chiplet 520 has a footprint that substantially matches a footprint of the underlying die substrate 505. In such embodiments, HBI pads 525 of the test chiplet 520 may be coupled to all of the HBI pads 515 of the die substrate 505. That is, a single test chiplet 520 may be used to test all of the populated nodes of the die substrate 505. While twenty two HBI pads 515/525 are shown, it is to be appreciated that hundreds or more, or thousands or more, HBI pads 515/525 may be provided between the test chiplet 520 and the die substrate 505.

As shown, bumps 527 may be provided on the backside of the test chiplet 520. The bumps 527 are for probing the test chiplet 520 during testing and/or debugging. That is, the bumps 527 may not be connected to any other device at the point of sale. Accordingly, the bumps 527 may remain substantially non-functional when left in the final device. By non-functional, embodiments disclosed herein may refer to bumps 527 that are not connected electrically to sockets or other electrical interfaces between substrates in a die module 550.

Referring now to FIG. 5B, a cross-sectional illustration of a die module 550 is shown, in accordance with an additional embodiment. The die module 550 may be substantially similar to the die module 550 in FIG. 5A, with the exception of the test chiplet 520 having a different form factor. For example, the test chiplet 520 may have a footprint that is substantially smaller than the footprint of the die substrate 505. Such an embodiment may be used when the test chiplet 520 is used to test one of the functional blocks of the die substrate 505. While a single test chiplet 520 is shown, it is to be appreciated that a plurality of test chiplets 520 may be provided on the backside surface of the die substrate 505 in some embodiments. The die module 550 in FIG. 5B may result in HBI pads 515 that are not coupled to any external device. As such, some of the HBI pads 515 may be electrically floating in a functioning device.

Referring now to FIG. 6A, a cross-sectional illustration of an electronic system 690 is shown, in accordance with an embodiment. In an embodiment, the electronic system 690 comprises a board 691. The board 691 may be a printed circuit board (PCB) or the like. In an embodiment, the board 691 is coupled to a package substrate 693 by interconnects 692. In the illustrated embodiment, the interconnects 692 are shown as being solder balls. However, it is to be appreciated that the interconnects 692 may be any second level interconnect (SLI) architecture, such as sockets, wires, or the like. In an embodiment, the package substrate 693 may be an organic substrate formed from a plurality of laminated buildup layers. Package substrate 693 may be cored or coreless. In an embodiment, conductive routing (e.g., pads, traces, vias, etc.) is provided through the package substrate 693.

In an embodiment, a die module 640 is coupled to the package substrate 693. The die module 640 may be coupled to the package substrate 693 by interconnects 644. The interconnects 644 may be FLIs in some embodiments. In an embodiment, the die module 640 comprises a die substrate 605. The die substrate 605 may be a silicon substrate or other semiconductor material. In an embodiment, routing layers 641 may be provided over a surface of the die substrate 605. HBI pads 615 may be provided over the routing layers 641.

In an embodiment, the die module 640 may further comprise a test chiplet 620. The test chiplet 620 may be provided between the die substrate 605 and the package substrate 693. Particularly, the test chiplet 620 may comprise HBI pads 625. The HBI pads 625 may be bonded to the HBI pads 615 of the die substrate 605. The HBI pads 625 may be coupled to FLIs 644 through TSVs through a thickness of the test chiplet 620.

In the illustrated embodiment, the test chiplet 620 is provided between the die substrate 605 and the package substrate 693, similar to the embodiment shown in FIG. 4A. However, it is to be appreciated that embodiments are not limited to such architectures. For example, the electronic system 690 may also include test chiplets 620 that are provided on a backside surface of the die substrate 605, similar to embodiments shown in FIGS. 5A and 5B.

In addition to test chiplets 620 coupled to the die substrate 605, the test chiplets 620 may be coupled to the package substrate 693. In such embodiments, the test chiplet 620 may have access to substantially more embedded memory (either directly integrated or via a high bandwidth attachment to a companion chiplet/microchiplet) than what is cost effective for volume manufacturing. Additionally, a mini-logic analyzer to intelligently digest the transactions that it has visibility to via its enhanced viewport signal connectivity may be provided. This would allow improved debuggability for early versions of the integrated chip/system in package.

Referring now to FIG. 6B, a cross-sectional illustration of an electronic system 690 is shown, in accordance with an additional embodiment. In an embodiment, a board 691 is coupled to a course metal layers 694 by interconnects 692. In the illustrated embodiment, the interconnects 692 are shown as being solder balls (e.g., C4 bumps). In an embodiment, a transistor layer 695 is over the course metal layers, and fine pitch metal layers 696 are provided over the transistor layer 695. In an embodiment, a test chiplet 620 is coupled to the fine pitch metal layers 696 through hybrid bonding 697 or the like.

FIG. 7 illustrates a computing device 700 in accordance with one implementation of the invention. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package that comprises a die module with base die and a test chiplet coupled to the base die with a HBI architecture, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be part of an electronic package that comprises a die module with base die and a test chiplet coupled to the base die with a HBI architecture, in accordance with embodiments described herein.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: an electronic package, comprising: a package substrate; a die module coupled to the package substrate, wherein the die module comprises: a die; and a chiplet coupled to the die, wherein the chiplet is coupled to the die with a hybrid bonding interconnect architecture.

Example 2: the electronic package of Example 1, wherein the die comprises a plurality of functional blocks.

Example 3: the electronic package of Example 2, wherein each functional block comprises one of a plurality of chiplets, wherein individual ones of the chiplets are coupled to the respective functional block by the hybrid bonding interconnect architecture.

Example 4: the electronic package of Examples 1-3, wherein the hybrid bonding interconnect architecture comprises first conductive pads surrounded by a first dielectric layer on the die and second conductive pads surrounded by a second dielectric layer on the chiplet, wherein the first conductive pads are bonded to the second conductive pads.

Example 5: the electronic package of Examples 1-4, wherein the chiplet comprises interconnects on a backside surface of the chiplet opposite from the hybrid bonding interconnect architecture.

Example 6: the electronic package of Example 5, wherein the interconnects are electrically floating.

Example 7: the electronic package of Example 5 or Example 6, further comprising: through substrate vias through the chiplet.

Example 8: the electronic package of Examples 1-7, wherein the chiplet is on a surface of the die opposite from the package substrate.

Example 9: the electronic package of Examples 1-8, wherein the chiplet is between the die and the package substrate.

Example 10: the electronic package of Examples 1-9, wherein a footprint of the chiplet is smaller than a footprint of the die.

Example 11: a chiplet, comprising: a substrate with a first surface and a second surface opposite from the first surfaces, wherein the substrate comprises a semiconductor material; first interconnects on the first surface of the substrate, wherein the first interconnects comprise a first pitch; a dielectric layer on the first surface of the substrate surrounding the first interconnects; second interconnects on the second surface of the substrate, wherein the second interconnects have a second pitch that is greater than the first pitch; and through substrate vias (TSVs) through the substrate, wherein the TSVs electrically couple the first interconnects to the second interconnects.

Example 12: the chiplet of Example 11, wherein the first pitch is approximately 10 μm or smaller.

Example 13: the chiplet of Example 11 or Example 12, wherein the chiplet is an active die.

Example 14: the chiplet of Example 13, wherein the substrate comprises circuitry for providing a test interface.

Example 15: the chiplet of Example 11 or Example 12, wherein the chiplet is a passive die.

Example 16: the chiplet of Examples 11-15, wherein the first interconnects and the dielectric layer are configured to provide a hybrid bonding interconnect architecture.

Example 17: the chiplet of Example 16, wherein the dielectric layer comprises silicon and oxygen, and wherein the first interconnects comprise copper.

Example 18: the chiplet of Examples 11-17, wherein the substrate comprises silicon.

Example 19: the chiplet of Examples 11-18, wherein the chiplet is a test chiplet configured to be attached to a functional block of a die.

Example 20: an electronic system, comprising: a board; a package substrate coupled to the board; a die coupled to the package substrate; and a chiplet coupled to the die with a hybrid bonding interconnect architecture, wherein the chiplet is a test device.

Example 21: the electronic system of Example 20, wherein the chiplet is between the die and the package substrate.

Example 22: the electronic system of Example 20, wherein the chiplet is over the die.

Example 23: the electronic system of Example 20, wherein the chiplet is on the package substrate.

Example 24: the electronic system of Examples 20-23, wherein individual interconnects of the hybrid bonding interconnect architecture have a pitch that is approximately 10 μm or less.

Example 25: the electronic system of Examples 20-24, further comprising a plurality of chiplets over the die.

Claims

1. An electronic package, comprising: a package substrate;a die module coupled to the package substrate, wherein the die module comprises: a die; anda chiplet coupled to the die, wherein the chiplet is coupled to the die with a hybrid bonding interconnect architecture.

2. The electronic package of claim 1, wherein the die comprises a plurality of functional blocks.

3. The electronic package of claim 2, wherein each functional block comprises one of a plurality of chiplets, wherein individual ones of the chiplets are coupled to the respective functional block by the hybrid bonding interconnect architecture.

4. The electronic package of claim 1, wherein the hybrid bonding interconnect architecture comprises first conductive pads surrounded by a first dielectric layer on the die and second conductive pads surrounded by a second dielectric layer on the chiplet, wherein the first conductive pads are bonded to the second conductive pads.

5. The electronic package of claim 1, wherein the chiplet comprises interconnects on a backside surface of the chiplet opposite from the hybrid bonding interconnect architecture.

6. The electronic package of claim 5, wherein the interconnects are electrically floating.

7. The electronic package of claim 5, further comprising: through substrate vias through the chiplet.

8. The electronic package of claim 1, wherein the chiplet is on a surface of the die opposite from the package substrate.

9. The electronic package of claim 1, wherein the chiplet is between the die and the package substrate.

10. The electronic package of claim 1, wherein a footprint of the chiplet is smaller than a footprint of the die.

11. A chiplet, comprising: a substrate with a first surface and a second surface opposite from the first surfaces, wherein the substrate comprises a semiconductor material;first interconnects on the first surface of the substrate, wherein the first interconnects comprise a first pitch;a dielectric layer on the first surface of the substrate surrounding the first interconnects;second interconnects on the second surface of the substrate, wherein the second interconnects have a second pitch that is greater than the first pitch; andthrough substrate vias (TSVs) through the substrate, wherein the TSVs electrically couple the first interconnects to the second interconnects.

12. The chiplet of claim 11, wherein the first pitch is approximately 10 μm or smaller.

13. The chiplet of claim 11, wherein the chiplet is an active die.

14. The chiplet of claim 13, wherein the substrate comprises circuitry for providing a test interface.

15. The chiplet of claim 11, wherein the chiplet is a passive die.

16. The chiplet of claim 11, wherein the first interconnects and the dielectric layer are configured to provide a hybrid bonding interconnect architecture.

17. The chiplet of claim 16, wherein the dielectric layer comprises silicon and oxygen, and wherein the first interconnects comprise copper.

18. The chiplet of claim 11, wherein the substrate comprises silicon.

19. The chiplet of claim 11, wherein the chiplet is a test chiplet configured to be attached to a functional block of a die.

20. An electronic system, comprising: a board;a package substrate coupled to the board;a die coupled to the package substrate; anda chiplet coupled to the die with a hybrid bonding interconnect architecture, wherein the chiplet is a test device.

21. The electronic system of claim 20, wherein the chiplet is between the die and the package substrate.

22. The electronic system of claim 20, wherein the chiplet is over the die.

23. The electronic system of claim 20, wherein the chiplet is on the package substrate.

24. The electronic system of claim 20, wherein individual interconnects of the hybrid bonding interconnect architecture have a pitch that is approximately 10 μm or less.

25. The electronic system of claim 20, further comprising a plurality of chiplets over the die.