Ghasi R. Agrawal

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
BISR mode to test the redundant elements and regular functional mem...
- Patent number 7,913,125
- Issue date Mar 22, 2011
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Accurate pin-based memory power model using arc-based characterization
- Patent number 7,640,152
- Issue date Dec 29, 2009
- LSI Corporation
- Jia-Lih J. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard BISR scheme allowing field repair and usage of reliability con...
- Patent number 7,536,611
- Issue date May 19, 2009
- LST Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for performing built-in-self-test routines using...
- Patent number 7,493,541
- Issue date Feb 17, 2009
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Accurate pin-based memory power model using arc-based characterization
- Patent number 7,376,541
- Issue date May 20, 2008
- LSI Logic Corporation
- Jia-Lih J. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfiguring a RAM to a ROM using layers of metallization
- Patent number 7,272,814
- Issue date Sep 18, 2007
- LSI Corporation
- Allen Faber
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for separating native, functional and test con...
- Patent number 7,260,700
- Issue date Aug 21, 2007
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for performing built-in self-test routines using...
- Patent number 7,260,758
- Issue date Aug 21, 2007
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing implementation suitable for built-in self-repair (BISR) mem...
- Patent number 7,185,243
- Issue date Feb 27, 2007
- LSI Logic Corporation
- Mukesh K. Puri
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
Converting dual port memory into 2 single port memories
- Patent number 7,180,819
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing semiconductor devices having built-in self repai...
- Patent number 7,076,699
- Issue date Jul 11, 2006
- LSI Logic Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan method for built-in-self-repair (BISR)
- Patent number 6,928,598
- Issue date Aug 9, 2005
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault repair controller for redundant memory integrated circuits
- Patent number 6,928,591
- Issue date Aug 9, 2005
- LSI Logic Corporation
- Mikhail I. Grinchuk
- G11 - INFORMATION STORAGE
Information Patent Grant
Sharing fuse blocks between memories in hard-BISR
- Patent number 6,898,143
- Issue date May 24, 2005
- LSI Logic Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-on state machine implementation with a counter to control the...
- Patent number 6,871,297
- Issue date Mar 22, 2005
- LSI Logic Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Grant
Row redundancy memory repair scheme with shift to eliminate timing...
- Patent number 6,870,782
- Issue date Mar 22, 2005
- LSI Logic Corporation
- Sifang Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-time scheme to reduce cycle time for memories
- Patent number 6,643,204
- Issue date Nov 4, 2003
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-repair of semiconductor memory with redundant row tes...
- Patent number 6,640,321
- Issue date Oct 28, 2003
- LSI Logic Corporation
- Johnnie A. Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory having column redundancy
- Patent number 6,507,524
- Issue date Jan 14, 2003
- LSI Logic Corporation
- Ghasi Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-time scheme to reduce cycle time for memories
- Patent number 6,483,754
- Issue date Nov 19, 2002
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for providing row redundancy with no timing penal...
- Patent number 6,438,046
- Issue date Aug 20, 2002
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power high density asynchronous memory architecture
- Patent number 6,404,700
- Issue date Jun 11, 2002
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Way to compensate the effect of coupling between bitlines in a mult...
- Patent number 6,370,078
- Issue date Apr 9, 2002
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory having column redundancy with no timing p...
- Patent number 6,366,508
- Issue date Apr 2, 2002
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Designing memory for testability to support scan capability in an a...
- Patent number 6,341,092
- Issue date Jan 22, 2002
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Laser fuse circuit design
- Patent number 6,288,598
- Issue date Sep 11, 2001
- LSI Logic Corporation
- Johnnie Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-port semiconductor memory and compiler having capacitance com...
- Patent number 6,233,197
- Issue date May 15, 2001
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing architecture with decreased precharge voltage levels
- Patent number 6,185,140
- Issue date Feb 6, 2001
- LSI Logic Corporation
- Ghasi Agrawal
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Accurate pin-based memory power model using arc-based characterization
- Publication number 20080208556
- Publication date Aug 28, 2008
- Jia-Lih J. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for separating native, functional and test con...
- Publication number 20060085701
- Publication date Apr 20, 2006
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Application
Reconfiguring a RAM to a ROM using upper layers of metallization
- Publication number 20060064664
- Publication date Mar 23, 2006
- Allen Faber
- G11 - INFORMATION STORAGE
Information Patent Application
Accurate pin-based memory power model using arc-based characterization
- Publication number 20060052996
- Publication date Mar 9, 2006
- Jia-Lih J. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
New hard BISR scheme allowing field repair and usage of reliability...
- Publication number 20050097383
- Publication date May 5, 2005
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Application
Novel bisr mode to test the redundant elements and regular function...
- Publication number 20050097417
- Publication date May 5, 2005
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Application
SHARING FUSE BLOCKS BETWEEN MEMORIES IN HARD-BISR
- Publication number 20050047253
- Publication date Mar 3, 2005
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Application
Row redundancy memory repair scheme with shift ot eliminate timing...
- Publication number 20040208065
- Publication date Oct 21, 2004
- Sifang Wu
- G11 - INFORMATION STORAGE
Information Patent Application
Fault repair controller for redundant memory integrated circuits
- Publication number 20040128593
- Publication date Jul 1, 2004
- LSI Logic Corporation
- Mikhail I. Grinchuk
- G11 - INFORMATION STORAGE
Information Patent Application
Power-on state machine implementation with a counter to control the...
- Publication number 20030196143
- Publication date Oct 16, 2003
- LSI Logic Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE

Ghasi R. Agrawal

Person

Patents Grantslast 30 patents

BISR mode to test the redundant elements and regular functional mem...

Accurate pin-based memory power model using arc-based characterization

Hard BISR scheme allowing field repair and usage of reliability con...

Method and system for performing built-in-self-test routines using...

Accurate pin-based memory power model using arc-based characterization

Reconfiguring a RAM to a ROM using layers of metallization

Method and apparatus for separating native, functional and test con...

Method and system for performing built-in self-test routines using...

Testing implementation suitable for built-in self-repair (BISR) mem...

Converting dual port memory into 2 single port memories

Method for testing semiconductor devices having built-in self repai...

Scan method for built-in-self-repair (BISR)

Fault repair controller for redundant memory integrated circuits

Sharing fuse blocks between memories in hard-BISR

Power-on state machine implementation with a counter to control the...

Row redundancy memory repair scheme with shift to eliminate timing...

Self-time scheme to reduce cycle time for memories

Built-in self-repair of semiconductor memory with redundant row tes...

Integrated circuit memory having column redundancy

Self-time scheme to reduce cycle time for memories

System and method for providing row redundancy with no timing penal...

Low power high density asynchronous memory architecture

Way to compensate the effect of coupling between bitlines in a mult...

Integrated circuit memory having column redundancy with no timing p...

Designing memory for testability to support scan capability in an a...

Laser fuse circuit design

Multi-port semiconductor memory and compiler having capacitance com...

Sensing architecture with decreased precharge voltage levels

Patents Applicationslast 30 patents

Accurate pin-based memory power model using arc-based characterization

Method and apparatus for separating native, functional and test con...

Reconfiguring a RAM to a ROM using upper layers of metallization

Accurate pin-based memory power model using arc-based characterization

New hard BISR scheme allowing field repair and usage of reliability...

Novel bisr mode to test the redundant elements and regular function...

SHARING FUSE BLOCKS BETWEEN MEMORIES IN HARD-BISR

Row redundancy memory repair scheme with shift ot eliminate timing...

Fault repair controller for redundant memory integrated circuits

Power-on state machine implementation with a counter to control the...