Gin Yee

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-invasive on-chip power measurement technique
- Patent number 11,215,664
- Issue date Jan 4, 2022
- Apple Inc.
- Ke Yun
- G01 - MEASURING TESTING
Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 11,023,403
- Issue date Jun 1, 2021
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 10,521,391
- Issue date Dec 31, 2019
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-deskewing IO method and system
- Patent number 7,688,925
- Issue date Mar 30, 2010
- ATI Technologies, Inc.
- Edward Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
IC analog debugging and calibration thereof
- Patent number 7,203,613
- Issue date Apr 10, 2007
- Sun Microsystems, Inc.
- Gin S. Yee
- G01 - MEASURING TESTING
Information Patent Grant
Compensation technique to mitigate aging effects in integrated circ...
- Patent number 7,129,800
- Issue date Oct 31, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded integrated circuit aging sensor system
- Patent number 7,054,787
- Issue date May 30, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Method for synchronizing clock and data signals
- Patent number 6,993,103
- Issue date Jan 31, 2006
- Sun Microsystems, Inc.
- David J. Greenhill
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Region-based voltage drop budgets for low-power design
- Patent number 6,976,235
- Issue date Dec 13, 2005
- Sun Microsystems, Inc.
- Sudhakar Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accuracy of timing analysis using region-based voltage drop budgets
- Patent number 6,971,079
- Issue date Nov 29, 2005
- Sun Microsystems, Inc.
- Gin Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip temperature measurement technique
- Patent number 6,934,652
- Issue date Aug 23, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Duty cycle corrector
- Patent number 6,882,196
- Issue date Apr 19, 2005
- Sun Microsystems, Inc.
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-die thermal monitoring technique
- Patent number 6,814,485
- Issue date Nov 9, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Clock frequency multiplier
- Patent number 6,815,991
- Issue date Nov 9, 2004
- Sun Microsystems, Inc.
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variation reduction technique for charge pump transistor aging
- Patent number 6,812,755
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Negative bias temperature instability correction technique for dela...
- Patent number 6,812,758
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual edge-triggered flip-flop design with asynchronous programmable...
- Patent number 6,720,813
- Issue date Apr 13, 2004
- Sun Microsystems, Inc.
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock detect indicator
- Patent number 6,707,320
- Issue date Mar 16, 2004
- Sun Microsystems, Inc.
- Pradeep Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deskewing global clock skew using localized DLLs
- Patent number 6,686,785
- Issue date Feb 3, 2004
- Sun Microsystems, Inc.
- Dean Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measuring skew using on-chip sampling
- Patent number 6,662,126
- Issue date Dec 9, 2003
- Sun Microsystems, Inc.
- Dean Liu
- G01 - MEASURING TESTING
Information Patent Grant
Frequency multiplier design
- Patent number 6,642,756
- Issue date Nov 4, 2003
- Sun Microsystems, Inc.
- Gin Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of high-performance CMOS design
- Patent number 6,549,038
- Issue date Apr 15, 2003
- University of Washington
- Carl Sechen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stretching, shortening, and/or removing a clock cycle
- Patent number 6,529,057
- Issue date Mar 4, 2003
- Sun Microsystems, Inc.
- Gin S. Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated shielding algorithm for dynamic circuits
- Patent number 6,510,545
- Issue date Jan 21, 2003
- Sun Microsystems, Inc.
- Gin S. Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock divider for analysis of all clock edges
- Patent number 6,441,656
- Issue date Aug 27, 2002
- Sun Microsystems, Inc.
- Gin S. Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual rail dynamic flip-flop with single evaluation path
- Patent number 6,265,923
- Issue date Jul 24, 2001
- Sun Microsystems, Inc.
- Chaim Amir
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Non-Invasive On-Chip Power Measurement Technique
- Publication number 20210396805
- Publication date Dec 23, 2021
- Apple Inc.
- Ke Yun
- G01 - MEASURING TESTING
Information Patent Application
CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH
- Publication number 20200183874
- Publication date Jun 11, 2020
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bit-deskewing IO method and system
- Publication number 20070036020
- Publication date Feb 15, 2007
- Edward Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Compensation technique to mitigate aging effects in integrated circ...
- Publication number 20050168255
- Publication date Aug 4, 2005
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip temperature measurement technique
- Publication number 20050114061
- Publication date May 26, 2005
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Single edge-triggered flip-flop design with asynchronous programmab...
- Publication number 20040187086
- Publication date Sep 23, 2004
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NEGATIVE BIAS TEMPERATURE INSTABILITY CORRECTION TECHNIQUE FOR DELA...
- Publication number 20040155696
- Publication date Aug 12, 2004
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
On-die thermal monitoring technique
- Publication number 20040146086
- Publication date Jul 29, 2004
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Embedded integrated circuit aging sensor System
- Publication number 20040148111
- Publication date Jul 29, 2004
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Variation reduction technique for charge pump transistor aging
- Publication number 20040145396
- Publication date Jul 29, 2004
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock frequency multiplier
- Publication number 20040135607
- Publication date Jul 15, 2004
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Region-based voltage drop budgets for low-power design
- Publication number 20040054979
- Publication date Mar 18, 2004
- Sudhakar Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accuracy of timing analysis using region-based voltage drop budgets
- Publication number 20040054975
- Publication date Mar 18, 2004
- Gin Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Duty cycle corrector
- Publication number 20040012428
- Publication date Jan 22, 2004
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock grid skew reduction technique using biasable delay drivers
- Publication number 20030163750
- Publication date Aug 28, 2003
- Pradeep Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock detect indicator
- Publication number 20030102899
- Publication date Jun 5, 2003
- Pradeep Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lock detect indicator for a phase locked loop
- Publication number 20030098720
- Publication date May 29, 2003
- Pradeep Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock grid skew reduction using a wire tree architecture
- Publication number 20030101423
- Publication date May 29, 2003
- Tyler Thorp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for synchronizing clock and data signals
- Publication number 20030076909
- Publication date Apr 24, 2003
- David J. Greenhill
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Deskewing global clock skew using localized DLLs
- Publication number 20030071669
- Publication date Apr 17, 2003
- Dean Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing clock skew by power supply isolation
- Publication number 20030037271
- Publication date Feb 20, 2003
- Dean Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Measuring skew using on-chip sampling
- Publication number 20030036862
- Publication date Feb 20, 2003
- Dean Liu
- G01 - MEASURING TESTING
Information Patent Application
Stretching, shortening, and/or removing a clock cycle
- Publication number 20020149411
- Publication date Oct 17, 2002
- Gin S. Yee
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Non-invasive on-chip power measurement technique

Chip to chip interface with scalable bandwidth

Chip to chip interface with scalable bandwidth

Bit-deskewing IO method and system

IC analog debugging and calibration thereof

Compensation technique to mitigate aging effects in integrated circ...

Embedded integrated circuit aging sensor system

Method for synchronizing clock and data signals

Region-based voltage drop budgets for low-power design

Accuracy of timing analysis using region-based voltage drop budgets

On-chip temperature measurement technique

Duty cycle corrector

On-die thermal monitoring technique

Clock frequency multiplier

Variation reduction technique for charge pump transistor aging

Negative bias temperature instability correction technique for dela...

Dual edge-triggered flip-flop design with asynchronous programmable...

Clock detect indicator

Deskewing global clock skew using localized DLLs

Measuring skew using on-chip sampling

Frequency multiplier design

Method of high-performance CMOS design

Stretching, shortening, and/or removing a clock cycle

Automated shielding algorithm for dynamic circuits

Clock divider for analysis of all clock edges

Dual rail dynamic flip-flop with single evaluation path

Patents Applicationslast 30 patents

Non-Invasive On-Chip Power Measurement Technique

CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH

Bit-deskewing IO method and system

Compensation technique to mitigate aging effects in integrated circ...

On-chip temperature measurement technique

Single edge-triggered flip-flop design with asynchronous programmab...

NEGATIVE BIAS TEMPERATURE INSTABILITY CORRECTION TECHNIQUE FOR DELA...

On-die thermal monitoring technique

Embedded integrated circuit aging sensor System

Variation reduction technique for charge pump transistor aging

Clock frequency multiplier

Region-based voltage drop budgets for low-power design

Accuracy of timing analysis using region-based voltage drop budgets

Duty cycle corrector

Clock grid skew reduction technique using biasable delay drivers

Clock detect indicator

Lock detect indicator for a phase locked loop

Clock grid skew reduction using a wire tree architecture

Method for synchronizing clock and data signals

Deskewing global clock skew using localized DLLs

Reducing clock skew by power supply isolation

Measuring skew using on-chip sampling

Stretching, shortening, and/or removing a clock cycle