Girishankar Gurumurthy

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Flip-flop circuit and scan chain using the same
- Patent number 10,126,363
- Issue date Nov 13, 2018
- Mediatek Inc.
- Wen-Yi Lin
- G01 - MEASURING TESTING
Information Patent Grant
Alternating tap-cell strategy in a standard cell logic block for ar...
- Patent number 9,419,014
- Issue date Aug 16, 2016
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density low power scan flip-flop
- Patent number 9,366,727
- Issue date Jun 14, 2016
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- G01 - MEASURING TESTING
Information Patent Grant
Low clock-power integrated clock gating cell
- Patent number 9,362,910
- Issue date Jun 7, 2016
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock gated flip-flops
- Patent number 9,331,680
- Issue date May 3, 2016
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High density flip-flop with asynchronous reset
- Patent number 8,578,224
- Issue date Nov 5, 2013
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- G01 - MEASURING TESTING
Information Patent Grant
Improving routability of integrated circuit design without impactin...
- Patent number 8,127,263
- Issue date Feb 28, 2012
- Texas Instruments Incorporated
- Pavan Vithal Torvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 8,112,737
- Issue date Feb 7, 2012
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Generation of standard cell library components with increased signa...
- Patent number 7,895,551
- Issue date Feb 22, 2011
- Texas Instruments Incorporated
- Dharin Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance and area scalable cell architecture technology
- Patent number 7,564,077
- Issue date Jul 21, 2009
- Texas Instruments Incorporated
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Representing data having multi-dimensional input vectors and corres...
- Patent number 7,483,819
- Issue date Jan 27, 2009
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 7,441,218
- Issue date Oct 21, 2008
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ISOLATION CIRCUIT WITHOUT ROUTED PATH COUPLED TO ALWAYS-ON POWER SU...
- Publication number 20220052694
- Publication date Feb 17, 2022
- MEDIATEK SINGAPORE PTE LTD
- Varinder Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP CIRCUIT AND SCAN CHAIN USING THE SAME
- Publication number 20180224505
- Publication date Aug 9, 2018
- MEDIATEK INC.
- Wen-Yi LIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER CLOCK GATED FLIP-FLOPS
- Publication number 20150070063
- Publication date Mar 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AR...
- Publication number 20140183602
- Publication date Jul 3, 2014
- Girishankar Gurumurthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW CLOCK-POWER INTEGRATED CLOCK GATING CELL
- Publication number 20140184271
- Publication date Jul 3, 2014
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH DENSITY LOW POWER SCAN FLIP-FLOP
- Publication number 20140189453
- Publication date Jul 3, 2014
- Girishankar Gurumurthy
- G01 - MEASURING TESTING
Information Patent Application
HIGH DENSITY FLIP-FLOP WITH ASYNCHRONOUS RESET
- Publication number 20130173977
- Publication date Jul 4, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Girishankar Gurumurthy
- G01 - MEASURING TESTING
Information Patent Application
ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA
- Publication number 20100199252
- Publication date Aug 5, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Pavan Vithal Torvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of standard cell library components with increased signa...
- Publication number 20090293023
- Publication date Nov 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Dharin Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES
- Publication number 20090013297
- Publication date Jan 8, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performance and Area Scalable Cell Architecture Technology
- Publication number 20070290270
- Publication date Dec 20, 2007
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Contact resistance and capacitance for semiconductor devices
- Publication number 20070277137
- Publication date Nov 29, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Representing Data Having Multi-dimensional Input Vectors and Corres...
- Publication number 20060123074
- Publication date Jun 8, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Girishankar GURUMURTHY
- G06 - COMPUTING CALCULATING COUNTING

Girishankar Gurumurthy

Person

Patents Grantslast 30 patents

Flip-flop circuit and scan chain using the same

Alternating tap-cell strategy in a standard cell logic block for ar...

High density low power scan flip-flop

Low clock-power integrated clock gating cell

Low power clock gated flip-flops

High density flip-flop with asynchronous reset

Improving routability of integrated circuit design without impactin...

Contact resistance and capacitance for semiconductor devices

Generation of standard cell library components with increased signa...

Performance and area scalable cell architecture technology

Representing data having multi-dimensional input vectors and corres...

Contact resistance and capacitance for semiconductor devices

Patents Applicationslast 30 patents

ISOLATION CIRCUIT WITHOUT ROUTED PATH COUPLED TO ALWAYS-ON POWER SU...

FLIP-FLOP CIRCUIT AND SCAN CHAIN USING THE SAME

LOW POWER CLOCK GATED FLIP-FLOPS

ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AR...

LOW CLOCK-POWER INTEGRATED CLOCK GATING CELL

HIGH DENSITY LOW POWER SCAN FLIP-FLOP

HIGH DENSITY FLIP-FLOP WITH ASYNCHRONOUS RESET

ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA

Generation of standard cell library components with increased signa...

CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES

Performance and Area Scalable Cell Architecture Technology

Contact resistance and capacitance for semiconductor devices

Representing Data Having Multi-dimensional Input Vectors and Corres...