Gobi R. Padmanabhan

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor wafer and die that include an integrated circuit and...
- Patent number 8,288,834
- Issue date Oct 16, 2012
- Texas Instruments Incorporated
- Gobi R. Padmanabhan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a metal interconnect with capacitive structures t...
- Patent number 7,790,602
- Issue date Sep 7, 2010
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MEMS semiconductor sensor device
- Patent number 7,633,131
- Issue date Dec 15, 2009
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a MOS transistor with a litho-less gate
- Patent number 7,482,228
- Issue date Jan 27, 2009
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sensor configuration for a capsule endoscope
- Patent number 7,399,274
- Issue date Jul 15, 2008
- National Semiconductor Corporation
- Brian Lester Halla
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of forming a semiconductor die with heat and electrical pipes
- Patent number 7,338,840
- Issue date Mar 4, 2008
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of selectively forming MEMS-based semiconductor devices at t...
- Patent number 7,329,555
- Issue date Feb 12, 2008
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Single-crystal silicon semiconductor structure
- Patent number 7,230,301
- Issue date Jun 12, 2007
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor sensor device using MEMS technology
- Patent number 7,192,819
- Issue date Mar 20, 2007
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a hermetic seal for silicon die with metal feed t...
- Patent number 7,109,571
- Issue date Sep 19, 2006
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die with heat and electrical pipes
- Patent number 7,075,133
- Issue date Jul 11, 2006
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of dicing a semiconductor wafer that substantially reduces t...
- Patent number 7,052,977
- Issue date May 30, 2006
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for dynamically adjusting field of view in a caps...
- Patent number 7,044,908
- Issue date May 16, 2006
- National Semiconductor Corporation
- Joseph Domenick Montalbo
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Multilevel metal interconnect and method of forming the interconnec...
- Patent number 7,042,092
- Issue date May 9, 2006
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a vertical MOS transistor
- Patent number 6,949,421
- Issue date Sep 27, 2005
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming the integrated circuit having a die with high Q i...
- Patent number 6,946,321
- Issue date Sep 20, 2005
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High Q inductor in multi-level interconnect
- Patent number 6,833,781
- Issue date Dec 21, 2004
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and method of forming the integrated circuit hav...
- Patent number 6,781,239
- Issue date Aug 24, 2004
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical MOS transistor
- Patent number 6,777,288
- Issue date Aug 17, 2004
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hermetic seal for silicon die with metal feed through structure
- Patent number 6,746,956
- Issue date Jun 8, 2004
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Radiation hardened MOS transistor
- Patent number 6,730,969
- Issue date May 4, 2004
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep submicron MOS transistor with increased threshold voltage
- Patent number 6,723,593
- Issue date Apr 20, 2004
- National Semiconductor Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon die with metal feed through structure
- Patent number 6,677,235
- Issue date Jan 13, 2004
- National Semiconductor Corporation
- Visvamohan Yegnashankaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable polysilicon gate array base cell architecture
- Patent number 5,917,207
- Issue date Jun 29, 1999
- LSI Logic Corporation
- Michael J. Colwell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic cells with bent gates and compressed minimum spacin...
- Patent number 5,874,754
- Issue date Feb 23, 1999
- LSI Logic Corporation
- Jasopin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a barrier metal technology for tungsten plug inter...
- Patent number 5,827,777
- Issue date Oct 27, 1998
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip having identification/encryption code
- Patent number 5,799,080
- Issue date Aug 25, 1998
- LSI Logic Corporation
- Gobi R. Padmanabhan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Non-rectangular MOS device configurations for gate array type integ...
- Patent number 5,796,130
- Issue date Aug 18, 1998
- LSI Logic Corporation
- Tim Carmichael
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a high electromigration resistant metallization s...
- Patent number 5,776,831
- Issue date Jul 7, 1998
- LSI Logic Corporation
- Gobi R. Padmanabhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip package with interconnect layers and routing and...
- Patent number 5,777,383
- Issue date Jul 7, 1998
- LSI Logic Corporation
- Mark P. Stager
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Configurations and methods to manufacture solar cell device with la...
- Publication number 20100288346
- Publication date Nov 18, 2010
- Gobi Ramakrishnan Padmanabhan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Gobi R. Padmanabhan

Person

Patents Grantslast 30 patents

Semiconductor wafer and die that include an integrated circuit and...

Method of forming a metal interconnect with capacitive structures t...

MEMS semiconductor sensor device

Method of forming a MOS transistor with a litho-less gate

Sensor configuration for a capsule endoscope

Method of forming a semiconductor die with heat and electrical pipes

Method of selectively forming MEMS-based semiconductor devices at t...

Single-crystal silicon semiconductor structure

Semiconductor sensor device using MEMS technology

Method of forming a hermetic seal for silicon die with metal feed t...

Semiconductor die with heat and electrical pipes

Method of dicing a semiconductor wafer that substantially reduces t...

Method and system for dynamically adjusting field of view in a caps...

Multilevel metal interconnect and method of forming the interconnec...

Method of forming a vertical MOS transistor

Method of forming the integrated circuit having a die with high Q i...

High Q inductor in multi-level interconnect

Integrated circuit and method of forming the integrated circuit hav...

Vertical MOS transistor

Hermetic seal for silicon die with metal feed through structure

Radiation hardened MOS transistor

Deep submicron MOS transistor with increased threshold voltage

Silicon die with metal feed through structure

Programmable polysilicon gate array base cell architecture

Microelectronic cells with bent gates and compressed minimum spacin...

Method of making a barrier metal technology for tungsten plug inter...

Semiconductor chip having identification/encryption code

Non-rectangular MOS device configurations for gate array type integ...

Method of forming a high electromigration resistant metallization s...

Semiconductor chip package with interconnect layers and routing and...

Patents Applicationslast 30 patents

Configurations and methods to manufacture solar cell device with la...