Grant Kloster

Person

Lake Oswego, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Frame reveals with maskless lithography in the manufacture of integ...
- Patent number 12,165,987
- Issue date Dec 10, 2024
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 11,532,724
- Issue date Dec 20, 2022
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 10,971,600
- Issue date Apr 6, 2021
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition utilizing sacrificial blocking layers for semi...
- Patent number 10,756,215
- Issue date Aug 25, 2020
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 10,396,176
- Issue date Aug 27, 2019
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective deposition utilizing sacrificial blocking layers for semi...
- Patent number 10,243,080
- Issue date Mar 26, 2019
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Precursor and process design for photo-assisted metal atomic layer...
- Patent number 9,932,671
- Issue date Apr 3, 2018
- Intel Corporation
- James M. Blackwell
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Forming layers of materials over small regions by selective chemica...
- Patent number 9,530,733
- Issue date Dec 27, 2016
- Intel Corporation
- Robert L. Bristol
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polymer interlayer dielectric and passivation materials for a micro...
- Patent number 8,154,121
- Issue date Apr 10, 2012
- Intel Corporation
- Kunal Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectric materials
- Patent number 7,658,975
- Issue date Feb 9, 2010
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectric materials
- Patent number 7,560,165
- Issue date Jul 14, 2009
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a porous dielectric layer and structures formed thereby
- Patent number 7,544,896
- Issue date Jun 9, 2009
- Intel Corporation
- Boyan Boyanov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectrics with silane coupling reagents
- Patent number 7,456,490
- Issue date Nov 25, 2008
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Aluminum incorporation in porous dielectric for improved mechanical...
- Patent number 7,422,020
- Issue date Sep 9, 2008
- Intel Corporation
- Vijayakumar Ramachandrarao
- C03 - GLASS MINERAL OR SLAG WOOL
Information Patent Grant
Organic-framework zeolite interlayer dielectrics
- Patent number 7,365,375
- Issue date Apr 29, 2008
- Intel Corporation
- Michael D. Goodner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin passivation layer on 3D devices
- Patent number 7,354,862
- Issue date Apr 8, 2008
- Intel Corporation
- Lawrence Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photosensitive dielectric layer
- Patent number 7,344,972
- Issue date Mar 18, 2008
- Intel Corporation
- Michael D. Goodner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectric material using plasma-induced surface pol...
- Patent number 7,335,586
- Issue date Feb 26, 2008
- Intel Corporation
- Vijayakumar S. RamachandraRao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air gap interconnect structure and method
- Patent number 7,332,406
- Issue date Feb 19, 2008
- Intel Corporation
- Hyun-Mog Park
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a stacked device filler
- Patent number 7,320,928
- Issue date Jan 22, 2008
- Intel Corporation
- Grant M. Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using zeolites to improve the mechanical strength of low-k interlay...
- Patent number 7,303,989
- Issue date Dec 4, 2007
- Intel Corporation
- Boyan Boyanov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of air gaps in an interconnect structure using a thin per...
- Patent number 7,294,568
- Issue date Nov 13, 2007
- Intel Corporation
- Michael D. Goodner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-K dielectric structure and method
- Patent number 7,294,934
- Issue date Nov 13, 2007
- Intel Corporation
- Grant M. Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectively converted inter-layer dielectric
- Patent number 7,239,019
- Issue date Jul 3, 2007
- Intel Corporation
- Jihperng Leu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming thin hard mask over air gap or porous dielectric
- Patent number 7,238,604
- Issue date Jul 3, 2007
- Intel Corporation
- Grant M. Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning a porous dielectric material
- Patent number 7,220,668
- Issue date May 22, 2007
- Intel Corporation
- Hyun-Mog Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealed three dimensional metal bonded integrated circuits
- Patent number 7,217,595
- Issue date May 15, 2007
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making semiconductor device using a novel interconnect cl...
- Patent number 7,214,594
- Issue date May 8, 2007
- Intel Corporation
- Lawrence D. Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition of diffusion barrier
- Patent number 7,214,605
- Issue date May 8, 2007
- Intel Corporation
- Shriram Ramanathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of bonding semiconductor devices
- Patent number 7,186,637
- Issue date Mar 6, 2007
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...
- Publication number 20250112077
- Publication date Apr 3, 2025
- Intel Corporation
- Feras Eid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER
- Publication number 20250108459
- Publication date Apr 3, 2025
- Intel Corporation
- Andrey Vyatskikh
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SELECTIVE LAYER TRANSFER
- Publication number 20250105046
- Publication date Mar 27, 2025
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS...
- Publication number 20240113039
- Publication date Apr 4, 2024
- Intel Corporation
- Tayseer Mahdi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRAME REVEALS WITH MASKLESS LITHOGRAPHY IN THE MANUFACTURE OF INTEG...
- Publication number 20220165677
- Publication date May 26, 2022
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20210143265
- Publication date May 13, 2021
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20200020786
- Publication date Jan 16, 2020
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMI...
- Publication number 20190189803
- Publication date Jun 20, 2019
- Intel Corporation
- Grant KLOSTER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20180219080
- Publication date Aug 2, 2018
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES
- Publication number 20180130707
- Publication date May 10, 2018
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMI...
- Publication number 20170330972
- Publication date Nov 16, 2017
- Intel Corporation
- GRANT KLOSTER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Precursor and Process Design for Photo-Assisted Metal Atomic Layer...
- Publication number 20170058401
- Publication date Mar 2, 2017
- Intel Corporation
- James M. BLACKWELL
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIV CHEMICAL...
- Publication number 20160190060
- Publication date Jun 30, 2016
- Intel Corporation
- Robert L. Bristol
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming ultra low dielectric constant porous dielectric films and s...
- Publication number 20090324928
- Publication date Dec 31, 2009
- Vijayakumar Ramachandrarao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLYMER INTERLAYER DIELECTRIC AND PASSIVATION MATERIALS FOR A MICRO...
- Publication number 20090212421
- Publication date Aug 27, 2009
- Kunal Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin passivation layer on 3D devices
- Publication number 20080142991
- Publication date Jun 19, 2008
- Lawrence Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Aluminum incorporation in porous dielectric for improved mechanical...
- Publication number 20080000875
- Publication date Jan 3, 2008
- Vijayakumar Ramachandrarao
- C03 - GLASS MINERAL OR SLAG WOOL
Information Patent Application
SEALED THREE DIMENSIONAL METAL BONDED INTEGRATED CIRCUITS
- Publication number 20070212815
- Publication date Sep 13, 2007
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of internal stress reduction in dielectric films with chemi...
- Publication number 20070123059
- Publication date May 31, 2007
- Michael G. Haverty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sealing porous dielectrics with silane coupling reagents
- Publication number 20070066079
- Publication date Mar 22, 2007
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming a dielectric layer using a hydrocarbon-containing precursor
- Publication number 20070032675
- Publication date Feb 8, 2007
- Robert P. Meagley
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method of patterning a porous dielectric material
- Publication number 20060292856
- Publication date Dec 28, 2006
- Hyun-Mog Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sealing porous dielectric material using plasma-induced surface pol...
- Publication number 20060281329
- Publication date Dec 14, 2006
- Vijayakumar S. RamachandraRao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin passivation layer on 3D devices
- Publication number 20060234473
- Publication date Oct 19, 2006
- Lawrence Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing internal film stress in dielectric film
- Publication number 20060220251
- Publication date Oct 5, 2006
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Organic-framework zeolite interlayer dielectrics
- Publication number 20060214303
- Publication date Sep 28, 2006
- Intel Corporation
- Michael D. Goodner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming a porous dielectric layer and structures formed thereby
- Publication number 20060145304
- Publication date Jul 6, 2006
- Boyan Boyanov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming a porous dielectric layer and structures formed thereby
- Publication number 20060145305
- Publication date Jul 6, 2006
- Intel Corporation
- Boyan Boyanov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selectively growing a polymeric material on a semiconductor substrate
- Publication number 20060118922
- Publication date Jun 8, 2006
- Michael D. Goodner
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Using zeolites to improve the mechanical strength of low-k interlay...
- Publication number 20060108687
- Publication date May 25, 2006
- Boyan Boyanov
- H01 - BASIC ELECTRIC ELEMENTS

Grant Kloster

Person

Patents Grantslast 30 patents

Frame reveals with maskless lithography in the manufacture of integ...

Selective gate spacers for semiconductor devices

Selective gate spacers for semiconductor devices

Selective deposition utilizing sacrificial blocking layers for semi...

Selective gate spacers for semiconductor devices

Selective deposition utilizing sacrificial blocking layers for semi...

Precursor and process design for photo-assisted metal atomic layer...

Forming layers of materials over small regions by selective chemica...

Polymer interlayer dielectric and passivation materials for a micro...

Sealing porous dielectric materials

Sealing porous dielectric materials

Forming a porous dielectric layer and structures formed thereby

Sealing porous dielectrics with silane coupling reagents

Aluminum incorporation in porous dielectric for improved mechanical...

Organic-framework zeolite interlayer dielectrics

Thin passivation layer on 3D devices

Photosensitive dielectric layer

Sealing porous dielectric material using plasma-induced surface pol...

Air gap interconnect structure and method

Method of forming a stacked device filler

Using zeolites to improve the mechanical strength of low-k interlay...

Formation of air gaps in an interconnect structure using a thin per...

Low-K dielectric structure and method

Selectively converted inter-layer dielectric

Forming thin hard mask over air gap or porous dielectric

Method of patterning a porous dielectric material

Sealed three dimensional metal bonded integrated circuits

Method of making semiconductor device using a novel interconnect cl...

Deposition of diffusion barrier

Method of bonding semiconductor devices

Patents Applicationslast 30 patents

ARCHITECTURES FOR FACILITATING BONDING IN WAFER-LEVEL SELECTIVE TRA...

PROTECTIVE DEBONDING STACK FOR SELECTIVE TRANSFER

SELECTIVE LAYER TRANSFER

BACKSIDE WAFER TREATMENTS TO REDUCE DISTORTIONS AND OVERLAY ERRORS...

FRAME REVEALS WITH MASKLESS LITHOGRAPHY IN THE MANUFACTURE OF INTEG...

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMI...

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES

SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMI...

Precursor and Process Design for Photo-Assisted Metal Atomic Layer...

FORMING LAYERS OF MATERIALS OVER SMALL REGIONS BY SELECTIV CHEMICAL...

Forming ultra low dielectric constant porous dielectric films and s...

POLYMER INTERLAYER DIELECTRIC AND PASSIVATION MATERIALS FOR A MICRO...

Thin passivation layer on 3D devices

Aluminum incorporation in porous dielectric for improved mechanical...

SEALED THREE DIMENSIONAL METAL BONDED INTEGRATED CIRCUITS

Methods of internal stress reduction in dielectric films with chemi...

Sealing porous dielectrics with silane coupling reagents

Forming a dielectric layer using a hydrocarbon-containing precursor

Method of patterning a porous dielectric material

Sealing porous dielectric material using plasma-induced surface pol...

Thin passivation layer on 3D devices

Reducing internal film stress in dielectric film

Organic-framework zeolite interlayer dielectrics

Forming a porous dielectric layer and structures formed thereby

Forming a porous dielectric layer and structures formed thereby

Selectively growing a polymeric material on a semiconductor substrate

Using zeolites to improve the mechanical strength of low-k interlay...