Patent Application
20060108687
Silica films, such as SiO2, are used in the microelectronics industry as dielectrics. A dielectric is described by its dielectric constant, more commonly known as the k-value of the dielectric. Dielectrics are used to isolate metal lines or layers from one another. Using a dielectric with a low dielectric constant helps to lessen crosstalk, the undesired capacitive or inductive interaction of one part of the circuit to another. As device density on integrated circuits increases, the metal lines become smaller, and the distance between metal layers decreases. As device geometries decrease, crosstalk effects become significant. Crosstalk effects can be reduced by lowering the k-value of the dielectric. Current technology uses dielectrics with a k-value between 2.5 and 4.0.
Silica has a dielectric constant of about 4.0, which is too high to be useful for next generation integrated circuits. Since air has a dielectric constant of 1.0, one way to lower the dielectric constant of silica is to incorporate voids or pores into the silica. There are several drawbacks to using this approach in an integrated circuit manufacturing process. First, porous dielectrics are generally not mechanically stable enough to support subsequent polishing operations. Additionally, the porous dielectric may allow transport of metal through the dielectric layer.
A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
The terms chip, integrated circuit, monolithic device, semiconductor device, and microelectronic device, are often used interchangeably in this field. The present invention is applicable to all of the above as they are generally understood in the field.
The terms contact and via both refer to structures for electrical connection of conductors from different interconnect levels. These terms are sometimes used in the art to describe both an opening in an insulator in which the structure will be completed, and the completed structure itself. For purposes of this disclosure, contact and via refer to the completed structure.
The expression low dielectric constant material refers to materials having a lower dielectric constant than silicon dioxide, which has a dielectric constant of 4. For example, organic polymers, amorphous fluorinated carbons, nanofoams, silicon based insulators containing organic polymers, carbon doped oxides of silicon and fluorine doped oxides of silicon have lower dielectric constants than silicon dioxide.
The letter k is often used to refer to dielectric constant. Similarly, the terms high-k and low-k are used in this field to refer to high dielectric constant and low dielectric constant respectively, where high means greater than the dielectric constant of silicon dioxide, and low means lower than the dielectric constant of silicon dioxide.
The parasitic capacitance seen by an interconnect line is a function of the distance to another conductor and the dielectric constant of the material between the conductors. However, increasing the spacing between interconnect lines increases the physical size, and thus the cost, of an integrated circuit. Therefore, in order to manufacture integrated circuits with low parasitic capacitance between interconnect lines, it is desirable to electrically isolate the conductors from each other with an insulator having a low dielectric constant.
One way to reduce the adverse effects of parasitic capacitance is to use low-k materials as insulators in advanced microelectronics. To achieve low dielectric constants, one can introduce porosity into the dielectric film. While increasing the porosity of a dielectric lowers the k-value of the film, it also lowers the mechanical strength of the film.
Because of their ordered nature, zeolites have significantly higher strengths than porous silicon oxide based materials such as porous SiO2, SiOF, and CDO. A zeolite is characterized by a high degree of ordered porosity, a high mechanical strength, and a low k-value.
The inherent porosity and permeability of zeolite dielectric layers poses significant integration challenges when using these porous dielectrics in the semiconductor manufacturing process. Chemical uptake may occur during etch or clean, significantly increasing the dielectric constant. Porosity may compromise the integrity of the metal barrier layer, leading to poor gap fill and interline leakage. Finally, permeability and ion-exchange properties can result in trapping of mobile ions, catalysts of undesirable reactions during barrier atomic layer deposition (ALD).
Damascene or dual damascene openings (308), which may include trench (308A) and/or via (308B) openings are formed in the porous zeolite layer. Trenches (308A) are formed in the zeolite layer (302), while via openings (308B) are formed through both the zeolite layer (302) and etch stop layer (306). A metal barrier layer (310) is formed over the damascene openings. The metal barrier layer may be formed by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).
When the metal barrier layer is deposited over the porous zeolite layer, metal deposits may be formed inside of the pores (312). This may lead to electrical shorts and/or a low breakdown voltage for the dielectric.
By impregnating the pores of the zeolite layer with a second low-k dielectric, the internal pores of the zeolite may be sealed, yet the zeolite layer will retain its desirable mechanical and low-k properties.
Next, as shown in block 404, the zeolite is impregnated with another low-k material. The low-k material may be a spin-on or plasma-deposited monomer or polymer, or may be another low-k material which is able to penetrate the pores of the zeolite. Alternately, the low-k material may be a polymer which is dissolved in another material, or may be a polymer which is part of a mixture with another material. Impregnation of the zeolite by the low-k material may be either complete or partial.
Once the pores of the zeolite have been partially or completely filled with a polymer or other low-k material, a damascene or dual damascene opening may be formed in the zeolite layer, as shown by block 406.
Next, as shown in block 408, a barrier layer metal may be formed over the damascene opening and the zeolite layer. In one embodiment, the barrier layer metal may be comprised of copper or an alloy of copper.
After the barrier layer metal has been formed, the damascene opening may be filled with a metal, such as, but not limited to copper or a copper alloy as shown in block 410. Thus, a damascene or dual damascene interconnect structure is formed.
After the dual damascene structures are formed, excess copper and barrier layer material may be removed, typically by a chemical mechanical polishing (CMP) process, as illustrated in block 412. Although dual damascene structures are described, damascene or other interconnect structures may be formed within the zeolite dielectric layer as well.
After the suspension has been treated to form a zeolite layer having polymer-impregnated pores, subsequent processing may occur, including formation of a damascene or dual damascene opening in the zeolite layer (block 456), formation of a barrier metal layer over the damascene opening and the zeolite layer (block 458), filling the damascene opening with a metal (block 460), and polishing the top surface of the metal (block 462). Each of these processes is described in greater detail above, in conjunction with
Polymerization of the precursor (506) may be initiated via thermal, plasma, or other means to facilitate polymerization during or subsequent to the impregnation process. In one embodiment, polymerization may be initiated by applying heat to the zeolite layer and the polymer precursor. In another embodiment, polymerization may be initiated by exposing the zeolite layer and the polymer precursor to a plasma.
In another embodiment, illustrated in
In another embodiment, the zeolite may be impregnated by using a hybrid method in which a macromonomer, such as oligomeric polyphenylene, is introduced into the zeolite matrix and then subsequently reacted to form a crosslinked network. The ability to modify the chemical properties of the zeolite host over a wide range by using specific additives makes it possible to tailor the zeolite to specific applications.
Next, as shown in
After the damascene or dual damascene structures are formed, excess copper and barrier layer material is removed, typically by a chemical mechanical polishing (CMP) process. The resulting structure is illustrated in
Thus, as described above, a porous zeolite ILD may be impregnated with a second low-k dielectric, such as a polymer, so as to seal the internal pores of the zeolite. The resulting structure may have a greater mechanical strength than a porous zeolite, because the pores have been filled with a polymer. Additionally, the k-value of the resulting structure may remain low because both the zeolite and polymer are low-k materials.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth herein. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
