Gregorio Spadea

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Common source EEPROM and flash memory
- Patent number RE40976
- Issue date Nov 17, 2009
- Albert Bergemont
- 365 - Static information storage and retrieval
Information Patent Grant
Non-volatile memory arrangement having nanocrystals
- Patent number 7,332,769
- Issue date Feb 19, 2008
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage EEPROM memory arrays
- Patent number 7,075,140
- Issue date Jul 11, 2006
- Gregorio Spadea
- G11 - INFORMATION STORAGE
Information Patent Grant
Common source EEPROM and flash memory
- Patent number 6,606,265
- Issue date Aug 12, 2003
- Virtual Silicon Technology, Inc.
- Albert Bergemont
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming an EEPROM cell together with transistor for peri...
- Patent number 6,451,652
- Issue date Sep 17, 2002
- The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust
- John Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ion implantation method
- Patent number 4,224,733
- Issue date Sep 30, 1980
- Fujitsu Limited
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned CMOS process for bulk silicon and insulating substrate...
- Patent number 4,047,284
- Issue date Sep 13, 1977
- National Semiconductor Corporation
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned CMOS for bulk silicon and insulating substrate device
- Patent number 4,047,285
- Issue date Sep 13, 1977
- National Semiconductor Corporation
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned CMOS process for bulk silicon and insulating substrate...
- Patent number 4,043,025
- Issue date Aug 23, 1977
- National Semiconductor Corporation
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned CMOS process for bulk silicon and insulating substrate...
- Patent number 3,983,620
- Issue date Oct 5, 1976
- National Semiconductor Corporation
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Non-Volatile Memory Including Insulated Gate Bipolar Transistors An...
- Publication number 20080128794
- Publication date Jun 5, 2008
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel applications for insulated gate bipolar transistors
- Publication number 20070040209
- Publication date Feb 22, 2007
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High voltage N-channel LDMOS devices built in a deep submicron CMOS...
- Publication number 20060284266
- Publication date Dec 21, 2006
- Stellar Kinetics LLC
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High voltage N-channel LDMOS devices built in a deep submicron CMOS...
- Publication number 20060284265
- Publication date Dec 21, 2006
- Stellar Kinetics LLC
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low voltage EEPROM memory arrays
- Publication number 20050110073
- Publication date May 26, 2005
- Gregorio Spadea
- G11 - INFORMATION STORAGE
Information Patent Application
Common source EEPROM and flash memory
- Publication number 20020176286
- Publication date Nov 28, 2002
- Virtual Silicon Technology, Inc.
- Albert Bergemont
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High voltage N-channel LDMOS devices built in a deep submicron CMOS...
- Publication number 20020171103
- Publication date Nov 21, 2002
- Virtual Silicon Technology, Inc.
- Gregorio Spadea
- H01 - BASIC ELECTRIC ELEMENTS

Gregorio Spadea

Person

Patents Grantslast 30 patents

Common source EEPROM and flash memory

Non-volatile memory arrangement having nanocrystals

Low voltage EEPROM memory arrays

Common source EEPROM and flash memory

Method for forming an EEPROM cell together with transistor for peri...

Ion implantation method

Self-aligned CMOS process for bulk silicon and insulating substrate...

Self-aligned CMOS for bulk silicon and insulating substrate device

Self-aligned CMOS process for bulk silicon and insulating substrate...

Self-aligned CMOS process for bulk silicon and insulating substrate...

Patents Applicationslast 30 patents

Non-Volatile Memory Including Insulated Gate Bipolar Transistors An...

Novel applications for insulated gate bipolar transistors

High voltage N-channel LDMOS devices built in a deep submicron CMOS...

High voltage N-channel LDMOS devices built in a deep submicron CMOS...

Low voltage EEPROM memory arrays

Common source EEPROM and flash memory

High voltage N-channel LDMOS devices built in a deep submicron CMOS...