Gregory G. Gaertner

Person

Eau Claire, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for user side scheduling in a multiprocessor o...
- Patent number 6,195,676
- Issue date Feb 27, 2001
- Silicon Graphics, Inc.
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Responding to service requests using minimal system-side context in...
- Patent number 5,390,329
- Issue date Feb 14, 1995
- Cray Research, Inc.
- Gregory G. Gaertner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual level scheduling of processes to multiple parallel regions of...
- Patent number 5,339,415
- Issue date Aug 16, 1994
- Cray Research, Inc.
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for communicating among processors having different speeds
- Patent number 5,202,988
- Issue date Apr 13, 1993
- SuperComputer Systems Limited Partnership
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast interrupt mechanism for interrupting processors in parallel in...
- Patent number 5,193,187
- Issue date Mar 9, 1993
- SuperComputer Systems Limited Partnership
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling a highly parallel multiprocessor...
- Patent number 5,179,702
- Issue date Jan 12, 1993
- SuperComputer Systems Limited Partnership
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for efficient non-virtual main memory management
- Patent number 5,159,678
- Issue date Oct 27, 1992
- SuperComputer Systems Limited Partnership
- Diane M. Wengelski
- G06 - COMPUTING CALCULATING COUNTING

Gregory G. Gaertner

Person

Patents Grantslast 30 patents

Method and apparatus for user side scheduling in a multiprocessor o...

Responding to service requests using minimal system-side context in...

Dual level scheduling of processes to multiple parallel regions of...

System for communicating among processors having different speeds

Fast interrupt mechanism for interrupting processors in parallel in...

System and method for controlling a highly parallel multiprocessor...

Method for efficient non-virtual main memory management