Gregory J. Mann

Person

Westmont, IL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay apparatus, nuclear medicine imaging device, delay method, and...
- Patent number 9,471,042
- Issue date Oct 18, 2016
- Toshiba Medical Systems Corporation
- Gregory J Mann
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for inserting delay, nuclear medicine imaging apparatus,...
- Patent number 9,063,520
- Issue date Jun 23, 2015
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Apparatus for programmable insertion delay to delay chain-based tim...
- Patent number 8,963,600
- Issue date Feb 24, 2015
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for analog-to-digital conversion with a high effective-sa...
- Patent number 8,866,654
- Issue date Oct 21, 2014
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for programmable metastable ring oscillator period for mu...
- Patent number 8,786,474
- Issue date Jul 22, 2014
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- G04 - HOROLOGY
Information Patent Grant
Apparatus for detection of a leading edge of a photo sensor output...
- Patent number 8,446,308
- Issue date May 21, 2013
- Kabushiki Kaisha Toshiba
- Kent Burr
- G01 - MEASURING TESTING
Information Patent Grant
Structure for hardware assisted bus state transition circuit using...
- Patent number 8,347,019
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for time to digital conversion
- Patent number 8,222,607
- Issue date Jul 17, 2012
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- G04 - HOROLOGY
Information Patent Grant
Apparatus for pipelined cyclic redundancy check circuit with multip...
- Patent number 8,136,010
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 8,132,136
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic critical path detector for digital logic circuit paths
- Patent number 7,941,772
- Issue date May 10, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for pipelined cyclic redundancy check circuit with multip...
- Patent number 7,886,210
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,865,789
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Serafino Bueti
- G01 - MEASURING TESTING
Information Patent Grant
Structure for task based debugger (transaction-event-job-trigger)
- Patent number 7,823,017
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task based debugger (transaction-event-job-trigger)
- Patent number 7,594,140
- Issue date Sep 22, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of manufacturing integrated circuits using pre-made and pre-...
- Patent number 7,519,941
- Issue date Apr 14, 2009
- International Business Machines Corporation
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Cyclic redundancy check generating circuit
- Patent number 7,328,396
- Issue date Feb 5, 2008
- International Business Machines Corporation
- Gregory J. Mann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for system-on-chip interconnect verification
- Patent number 7,313,738
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing an integrated circuit IP core...
- Patent number 7,308,668
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network for decreasing transmit link layer core speed
- Patent number 7,254,647
- Issue date Aug 7, 2007
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel parallel CRC generation and checking circuit
- Patent number 7,225,387
- Issue date May 29, 2007
- International Business Machines Corporation
- Ming-i M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Communication systems and methods using microelectronics power dist...
- Patent number 7,129,821
- Issue date Oct 31, 2006
- International Business Machines Corporation
- Serafino Bueti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable cyclic redundancy check circuit
- Patent number 7,103,832
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Network for increasing transmit link layer core speed
- Patent number 6,665,754
- Issue date Dec 16, 2003
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor for determining physical lane skew order
- Patent number 6,625,675
- Issue date Sep 23, 2003
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DELAY APPARATUS, NUCLEAR MEDICINE IMAGING DEVICE, DELAY METHOD, AND...
- Publication number 20150370223
- Publication date Dec 24, 2015
- KABUSHIKI KAISHA TOSHIBA
- Gregory J. MANN
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR INSERTING DELAY, NUCLEAR MEDICINE IMAGING APPARATUS,...
- Publication number 20140330117
- Publication date Nov 6, 2014
- Kabushiki Kaisha Toshiba
- Gregory J. Mann
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR PROGRAMMABLE INSERTION DELAY TO DELAY CHAIN-BASED TIM...
- Publication number 20140247078
- Publication date Sep 4, 2014
- TOSHIBA MEDICAL SYSTEMS CORPORATION
- Gregory J. MANN
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR DETECTION OF A LEADING EDGE OF A PHOTO SENSOR OUTPUT...
- Publication number 20120268303
- Publication date Oct 25, 2012
- TOSHIBA MEDICAL SYSTEMS CORPORATION
- KENT BURR
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION WITH A HIGH EFFECTIVE-SA...
- Publication number 20120268105
- Publication date Oct 25, 2012
- TOSHIBA MEDICAL SYSTEMS CORPORATION
- Gregory J. MANN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR TIME TO DIGITAL CONVERSION
- Publication number 20120104259
- Publication date May 3, 2012
- TOSHIBA MEDICAL SYSTEMS CORPORATION
- Gregory J. MANN
- G04 - HOROLOGY
Information Patent Application
APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...
- Publication number 20090164865
- Publication date Jun 25, 2009
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...
- Publication number 20090132732
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...
- Publication number 20090132747
- Publication date May 21, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044160
- Publication date Feb 12, 2009
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
- Publication number 20090044054
- Publication date Feb 12, 2009
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...
- Publication number 20080282015
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TR...
- Publication number 20080215923
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for system-on-chip interconnect verification
- Publication number 20080215945
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...
- Publication number 20080195915
- Publication date Aug 14, 2008
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...
- Publication number 20080183941
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...
- Publication number 20070245290
- Publication date Oct 18, 2007
- Serafino Bueti
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULT...
- Publication number 20070101332
- Publication date May 3, 2007
- International Business Machines Corporation
- Adam Joseph Courchesne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE...
- Publication number 20070006108
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
- Publication number 20060242524
- Publication date Oct 26, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR...
- Publication number 20060095905
- Publication date May 4, 2006
- International Business Machines Corporation
- Adam J. Courchesne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...
- Publication number 20060041705
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Serafino Bueti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DIST...
- Publication number 20060038444
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Serafino Bueti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT
- Publication number 20050268209
- Publication date Dec 1, 2005
- International Business Machines Corporation
- Gregory J. Mann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multilevel parallel CRC generation and checking circuit
- Publication number 20050172205
- Publication date Aug 4, 2005
- International Business Machines Corporation
- Ming-i M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scalable cyclic redundancy check circuit
- Publication number 20050138523
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Todd E. Leonard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Network for decreasing transmit link layer core speed
- Publication number 20040210687
- Publication date Oct 21, 2004
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network for increasing transmit link layer core speed
- Publication number 20020138674
- Publication date Sep 26, 2002
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor for determining physical lane skew order
- Publication number 20020138675
- Publication date Sep 26, 2002
- International Business Machines Corporation
- Gregory J. Mann
- G06 - COMPUTING CALCULATING COUNTING

Gregory J. Mann

Person

Patents Grantslast 30 patents

Delay apparatus, nuclear medicine imaging device, delay method, and...

Apparatus for inserting delay, nuclear medicine imaging apparatus,...

Apparatus for programmable insertion delay to delay chain-based tim...

Apparatus for analog-to-digital conversion with a high effective-sa...

Apparatus for programmable metastable ring oscillator period for mu...

Apparatus for detection of a leading edge of a photo sensor output...

Structure for hardware assisted bus state transition circuit using...

Apparatus for time to digital conversion

Apparatus for pipelined cyclic redundancy check circuit with multip...

Dynamic critical path detector for digital logic circuit paths

Dynamic critical path detector for digital logic circuit paths

Apparatus for pipelined cyclic redundancy check circuit with multip...

System and method for system-on-chip interconnect verification

Structure for task based debugger (transaction-event-job-trigger)

Task based debugger (transaction-event-job-trigger)

Method of manufacturing integrated circuits using pre-made and pre-...

Cyclic redundancy check generating circuit

System and method for system-on-chip interconnect verification

Apparatus and method for implementing an integrated circuit IP core...

Network for decreasing transmit link layer core speed

Multilevel parallel CRC generation and checking circuit

Communication systems and methods using microelectronics power dist...

Scalable cyclic redundancy check circuit

Network for increasing transmit link layer core speed

Processor for determining physical lane skew order

Patents Applicationslast 30 patents

DELAY APPARATUS, NUCLEAR MEDICINE IMAGING DEVICE, DELAY METHOD, AND...

APPARATUS FOR INSERTING DELAY, NUCLEAR MEDICINE IMAGING APPARATUS,...

APPARATUS FOR PROGRAMMABLE INSERTION DELAY TO DELAY CHAIN-BASED TIM...

APPARATUS FOR DETECTION OF A LEADING EDGE OF A PHOTO SENSOR OUTPUT...

APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION WITH A HIGH EFFECTIVE-SA...

APPARATUS FOR TIME TO DIGITAL CONVERSION

APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...

UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN IN...

STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRON...

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS

DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT...

DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TR...

System and method for system-on-chip interconnect verification

APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIP...

HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE ME...

METHOD OF MANUFACTURING INTEGRATED CIRCUITS USING PRE-MADE AND PRE-...

METHOD AND APPARATUS FOR RESOURCE-BASED THREAD ALLOCATION IN A MULT...

APPARATUS AND METHOD FOR IMPLEMENTING AN INTEGRATED CIRCUIT IP CORE...

SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION

METHOD AND APPARATUS FOR SERVICING THREADS WITHIN A MULTI-PROCESSOR...

SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DE...

COMMUNICATION SYSTEMS AND METHODS USING MICROELECTRONICS POWER DIST...

CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT

Multilevel parallel CRC generation and checking circuit

Scalable cyclic redundancy check circuit

Network for decreasing transmit link layer core speed

Network for increasing transmit link layer core speed

Processor for determining physical lane skew order