Guoxiang NING

Person

Ballston Lake, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gap fill void and connection structures
- Patent number 11,651,992
- Issue date May 16, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Haigou Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM bit cells formed with dummy structures
- Patent number 11,037,937
- Issue date Jun 15, 2021
- GLOBALFOUNDRIES U.S. INC.
- Meixiong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin-based anti-fuse device for integrated circuit (IC) products, me...
- Patent number 10,957,701
- Issue date Mar 23, 2021
- GLOBALFOUNDRIES U.S. INC.
- HongLiang Shen
- G11 - INFORMATION STORAGE
Information Patent Grant
Gap fill void and connection structures
- Patent number 10,923,388
- Issue date Feb 16, 2021
- GLOBALFOUNDRIES U.S. INC.
- Haigou Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnects separated by a dielectric region formed using removab...
- Patent number 10,896,874
- Issue date Jan 19, 2021
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anti-fuse for an integrated circuit (IC) product and method of maki...
- Patent number 10,892,222
- Issue date Jan 12, 2021
- GLOBALFOUNDRIES Inc.
- Erfeng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double pass diluted ultraviolet reticle inspection
- Patent number 10,816,483
- Issue date Oct 27, 2020
- GLOBALFOUNDRIES Inc.
- Jed H. Rankin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device/health of line (HOL) aware eBeam based overlay (EBO OVL) str...
- Patent number 10,804,170
- Issue date Oct 13, 2020
- GLOBALFOUNDRIES Inc.
- Hongliang Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnects with non-mandrel cuts formed by early block patterning
- Patent number 10,777,413
- Issue date Sep 15, 2020
- GLOBALFOUNDRIES Inc.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chamferless interconnect vias of semiconductor devices
- Patent number 10,770,344
- Issue date Sep 8, 2020
- GLOBALFOUNDRIES Inc.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlling back-end-of-line dimensions of semiconductor devices
- Patent number 10,727,120
- Issue date Jul 28, 2020
- GLOBALFOUNDRIES Inc.
- Sean X Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anti-fuse with self aligned via patterning
- Patent number 10,714,422
- Issue date Jul 14, 2020
- GLOBALFOUNDRIES Inc.
- Xiaoqiang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned quadruple patterning pitch walking solution
- Patent number 10,642,160
- Issue date May 5, 2020
- GLOBALFOUNDRIES Inc.
- Lei Sun
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Overlay mark structures
- Patent number 10,627,720
- Issue date Apr 21, 2020
- GLOBALFOUNDRIES Inc.
- Lei Sun
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Overlay structures
- Patent number 10,483,214
- Issue date Nov 19, 2019
- GLOBALFOUNDRIES Inc.
- Xintuo Dai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
FinFET cut isolation opening revision to compensate for overlay ina...
- Patent number 10,423,078
- Issue date Sep 24, 2019
- GLOBALFOUNDRIES Inc.
- Hongliang Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Geometry vectorization for mask process correction
- Patent number 10,386,726
- Issue date Aug 20, 2019
- GLOBALFOUNDRIES Inc.
- Liang Cao
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dummy assist features for pattern support
- Patent number 10,332,745
- Issue date Jun 25, 2019
- GLOBALFOUNDRIES Inc.
- Lei Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET cut isolation opening revision to compensate for overlay ina...
- Patent number 10,324,381
- Issue date Jun 18, 2019
- GLOBALFOUNDRIES Inc.
- Hongliang Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-aligned metal wire on contact structure and method for forming...
- Patent number 10,199,271
- Issue date Feb 5, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selective re-routing of selected areas in a target layer...
- Patent number 10,002,827
- Issue date Jun 19, 2018
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Metrology pattern layout and method of use thereof
- Patent number 9,864,831
- Issue date Jan 9, 2018
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method wherein test cells and dummy cells are included into a layou...
- Patent number 9,817,940
- Issue date Nov 14, 2017
- GLOBALFOUNDRIES Inc.
- Guido Ueberreiter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monitoring pattern for devices
- Patent number 9,791,772
- Issue date Oct 17, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method wherein test cells and dummy cells are included into a layou...
- Patent number 9,672,312
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Inc.
- Guido Ueberreiter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for selective re-routing of selected areas in a target layer...
- Patent number 9,672,313
- Issue date Jun 6, 2017
- GLOBALFOUNDRIES Inc.
- Guoxiang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device resolution enhancement by etching multiple sid...
- Patent number 9,658,531
- Issue date May 23, 2017
- GLOBALFOUNDRIES, INC.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Multiple threshold convergent OPC model
- Patent number 9,645,486
- Issue date May 9, 2017
- GLOBALFOUNDRIES Inc.
- Chin Teong Lim
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Alternating space decomposition in circuit structure fabrication
- Patent number 9,606,432
- Issue date Mar 28, 2017
- GLOBALFOUNDRIES, INC.
- Guoxiang Ning
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Reticle, system comprising a plurality of reticles and method for t...
- Patent number 9,535,319
- Issue date Jan 3, 2017
- GLOBALFOUNDRIES Inc.
- Guido Ueberreiter
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
SRAM BIT CELLS FORMED WITH DUMMY STRUCTURES
- Publication number 20210151443
- Publication date May 20, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Meixiong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GAP FILL VOID AND CONNECTION STRUCTURES
- Publication number 20210134658
- Publication date May 6, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Haigou HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS SEPARATED BY A DIELECTRIC REGION FORMED USING REMOVAB...
- Publication number 20200312764
- Publication date Oct 1, 2020
- GLOBALFOUNDRIES INC.
- Guoxiang Ning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE/HEALTH OF LINE (HOL) AWARE EBEAM BASED OVERLAY (EBO OVL) STR...
- Publication number 20200294868
- Publication date Sep 17, 2020
- GLOBALFOUNDRIES INC.
- Hongliang SHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GAP FILL VOID AND CONNECTION STRUCTURES
- Publication number 20200235002
- Publication date Jul 23, 2020
- GLOBALFOUNDRIES INC.
- Haigou HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES
- Publication number 20200219763
- Publication date Jul 9, 2020
- GLOBALFOUNDRIES INC.
- YUPING REN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE PASS DILUTED ULTRAVIOLET RETICLE INSPECTION
- Publication number 20200209166
- Publication date Jul 2, 2020
- GLOBALFOUNDRIES INC.
- Jed H. Rankin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTI-FUSE WITH SELF ALIGNED VIA PATTERNING
- Publication number 20200118927
- Publication date Apr 16, 2020
- GLOBALFOUNDRIES INC.
- Xiaoqiang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTROLLING BACK-END-OF-LINE DIMENSIONS OF SEMICONDUCTOR DEVICES
- Publication number 20200066586
- Publication date Feb 27, 2020
- GLOBALFOUNDRIES INC.
- SEAN X LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTS WITH NON-MANDREL CUTS FORMED BY EARLY BLOCK PATTERNING
- Publication number 20200020531
- Publication date Jan 16, 2020
- GLOBALFOUNDRIES INC.
- Yuping Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTOLITHOGRAPHY SYSTEM AND METHOD USING A RETICLE WITH MULTIPLE DI...
- Publication number 20190278166
- Publication date Sep 12, 2019
- GLOBALFOUNDRIES INC.
- Lei Sun
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
SELF-ALIGNED QUADRUPLE PATTERNING PITCH WALKING SOLUTION
- Publication number 20190271918
- Publication date Sep 5, 2019
- GLOBALFOUNDRIES INC.
- Lei Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OVERLAY STRUCTURES
- Publication number 20190206802
- Publication date Jul 4, 2019
- GLOBALFOUNDRIES INC.
- Xintuo DAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GEOMETRY VECTORIZATION FOR MASK PROCESS CORRECTION
- Publication number 20190101834
- Publication date Apr 4, 2019
- GLOBALFOUNDRIES INC.
- Liang Cao
- G05 - CONTROLLING REGULATING
Information Patent Application
OVERLAY MARK STRUCTURES
- Publication number 20190056671
- Publication date Feb 21, 2019
- GLOBALFOUNDRIES INC.
- Lei Sun
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
DUMMY ASSIST FEATURES FOR PATTERN SUPPORT
- Publication number 20180337045
- Publication date Nov 22, 2018
- GLOBALFOUNDRIES INC.
- Lei Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOU...
- Publication number 20170235866
- Publication date Aug 17, 2017
- GLOBALFOUNDRIES INC.
- Guido Ueberreiter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...
- Publication number 20170186687
- Publication date Jun 29, 2017
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN CLASSIFICATION BASED PROXIMITY CORRECTIONS FOR RETICLE FABR...
- Publication number 20160363853
- Publication date Dec 15, 2016
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...
- Publication number 20160328511
- Publication date Nov 10, 2016
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOU...
- Publication number 20160328510
- Publication date Nov 10, 2016
- GLOBALFOUNDRIES INC.
- Guido Ueberreiter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR T...
- Publication number 20160291457
- Publication date Oct 6, 2016
- GLOBALFOUNDRIES INC.
- Guido Ueberreiter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF
- Publication number 20160196381
- Publication date Jul 7, 2016
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE THRESHOLD CONVERGENT OPC MODEL
- Publication number 20160161840
- Publication date Jun 9, 2016
- GLOBALFOUNDRIES INC.
- Chin Teong LIM
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
ACHIEVING A CRITICAL DIMENSION TARGET BASED ON RESIST CHARACTERISTICS
- Publication number 20160125121
- Publication date May 5, 2016
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALTERNATING SPACE DECOMPOSITION IN CIRCUIT STRUCTURE FABRICATION
- Publication number 20160124308
- Publication date May 5, 2016
- GLOBALFOUNDRIES, Inc.
- Guoxiang NING
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
- Publication number 20160079180
- Publication date Mar 17, 2016
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION
- Publication number 20150310157
- Publication date Oct 29, 2015
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION
- Publication number 20150287651
- Publication date Oct 8, 2015
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF
- Publication number 20150278426
- Publication date Oct 1, 2015
- GLOBALFOUNDRIES INC.
- Guoxiang NING
- G06 - COMPUTING CALCULATING COUNTING

Guoxiang NING

Person

Patents Grantslast 30 patents

Gap fill void and connection structures

SRAM bit cells formed with dummy structures

Fin-based anti-fuse device for integrated circuit (IC) products, me...

Gap fill void and connection structures

Interconnects separated by a dielectric region formed using removab...

Anti-fuse for an integrated circuit (IC) product and method of maki...

Double pass diluted ultraviolet reticle inspection

Device/health of line (HOL) aware eBeam based overlay (EBO OVL) str...

Interconnects with non-mandrel cuts formed by early block patterning

Chamferless interconnect vias of semiconductor devices

Controlling back-end-of-line dimensions of semiconductor devices

Anti-fuse with self aligned via patterning

Self-aligned quadruple patterning pitch walking solution

Overlay mark structures

Overlay structures

FinFET cut isolation opening revision to compensate for overlay ina...

Geometry vectorization for mask process correction

Dummy assist features for pattern support

FinFET cut isolation opening revision to compensate for overlay ina...

Self-aligned metal wire on contact structure and method for forming...

Method for selective re-routing of selected areas in a target layer...

Metrology pattern layout and method of use thereof

Method wherein test cells and dummy cells are included into a layou...

Monitoring pattern for devices

Method wherein test cells and dummy cells are included into a layou...

Method for selective re-routing of selected areas in a target layer...

Semiconductor device resolution enhancement by etching multiple sid...

Multiple threshold convergent OPC model

Alternating space decomposition in circuit structure fabrication

Reticle, system comprising a plurality of reticles and method for t...

Patents Applicationslast 30 patents

SRAM BIT CELLS FORMED WITH DUMMY STRUCTURES

GAP FILL VOID AND CONNECTION STRUCTURES

INTERCONNECTS SEPARATED BY A DIELECTRIC REGION FORMED USING REMOVAB...

DEVICE/HEALTH OF LINE (HOL) AWARE EBEAM BASED OVERLAY (EBO OVL) STR...

GAP FILL VOID AND CONNECTION STRUCTURES

CHAMFERLESS INTERCONNECT VIAS OF SEMICONDUCTOR DEVICES

DOUBLE PASS DILUTED ULTRAVIOLET RETICLE INSPECTION

ANTI-FUSE WITH SELF ALIGNED VIA PATTERNING

CONTROLLING BACK-END-OF-LINE DIMENSIONS OF SEMICONDUCTOR DEVICES

INTERCONNECTS WITH NON-MANDREL CUTS FORMED BY EARLY BLOCK PATTERNING

PHOTOLITHOGRAPHY SYSTEM AND METHOD USING A RETICLE WITH MULTIPLE DI...

SELF-ALIGNED QUADRUPLE PATTERNING PITCH WALKING SOLUTION

OVERLAY STRUCTURES

GEOMETRY VECTORIZATION FOR MASK PROCESS CORRECTION

OVERLAY MARK STRUCTURES

DUMMY ASSIST FEATURES FOR PATTERN SUPPORT

METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOU...

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...

PATTERN CLASSIFICATION BASED PROXIMITY CORRECTIONS FOR RETICLE FABR...

METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER...

METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOU...

RETICLE, SYSTEM COMPRISING A PLURALITY OF RETICLES AND METHOD FOR T...

METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF

MULTIPLE THRESHOLD CONVERGENT OPC MODEL

ACHIEVING A CRITICAL DIMENSION TARGET BASED ON RESIST CHARACTERISTICS

ALTERNATING SPACE DECOMPOSITION IN CIRCUIT STRUCTURE FABRICATION

OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION

MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION

OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION

METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF