Patent Application
20200066586
The presently disclosed subject matter relates generally to the fabrication of semiconductor devices, and more particularly to a method of controlling dimensions of back-end-of-line (BEOL) structures and the resulting device.
The ongoing progress in the semiconductor industry is continuing to lead to greater device miniaturization. Device miniaturization is enabled by increasing structure pattern density and enhancing functionality that effectively reduces the cost per chip. As the geometric limits of the semiconductor structures are pushed against process technology limits, the dimensions of the structures formed in an integrated circuit have shrunk to the point where tighter tolerances and precise process controls are critical to further device miniaturization and fabrication success.
However, with smaller geometries, precise dimension control has become increasingly difficult. For interconnect via fabrication, many processes are inadequate to produce the needed smaller geometries and the required structural integrity. It is undesirable to have tapered profiles forming at the top and/or sidewalls of the interconnect vias, as such profiles may cause undesirable deviation from electrical property design specifications and thereby compromise the quality and reliability of the semiconductor device. The conventional approach to reduce the dimensions of semiconductor devices is to rely on improvements to the lithographic process. Such improvements can be time consuming and expensive, often requiring additional process steps and/or expensive new equipment.
It is, therefore, desirable to provide a method that has improved process control for fabricating structures with smaller dimensions, in particular, back-end-of-line interconnects.
To achieve the foregoing and other aspects of the present disclosure, a method of controlling the dimensions of back-end-of-line structures and the resulting device are disclosed.
According to an aspect of the present disclosure, a method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.
According to another aspect of the present disclosure, a semiconductor device with an interconnect structure is provided. The interconnect structure includes a metallization layer having at least one metal line, a dielectric layer, a metal ring and a via opening. The dielectric layer is formed on the metallization layer. The metal ring is formed on the dielectric layer. The via opening is formed in the dielectric layer, wherein the via opening has a top opening with the metal ring located at a shoulder portion thereof and a bottom opening that is aligned to the metal line.
The embodiments of the present disclosure will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the device. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the device. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
The following detailed description is exemplary in nature and is not intended to limit the device or the application and uses of the device. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the device or the following detailed description.
A method and a structure are disclosed for fabricating a back-end-of-line (BEOL) interconnect structure and controlling a top dimension of a via opening in a semiconductor device. The control of the top dimension is accomplished by growing a metal shoulder at a top portion of the via opening. The metal shoulder provides a controllable aperture dimension for forming the via opening. This method in the present disclosure provides an attractive solution for controlling the top dimension of the via opening, which overcomes the limitations of the conventional lithography and/or etch processes to reliably fabricate features of small geometries.
The interconnect structure is made of a conductive material and the conductive material is preferably copper (Cu) in advanced interconnect structures, but alternatively, may be cobalt (Co) or other similar conductive materials. A diffusion barrier liner (not shown) may be used to line the interconnects, and such liners are typically made up of tantalum (Ta), titanium (Ti), tungsten (W) or nitrides of these metals. It should be understood that the number and placements of the interconnect vias may vary according to the specific design of each semiconductor device.
The second dielectric layer 222, the third dielectric layer 224, the first hardmask layer 226, the fourth dielectric layer 228 and the second hardmask layer 240 may be deposited using conventional deposition processes, including physical vapor deposition (PVD), chemical vapor deposition (CVD), pulsed CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD) or combined methods. In one embodiment of the device, the first dielectric layer 212, the third dielectric layer 224 and the fourth dielectric layer 228 compose of similar low-k or ultra-low-k dielectric material and their thicknesses may vary according to the specific design of the semiconductor device. The second dielectric layer 222 is a capping layer, for example, a nitrogen-doped barrier low-k (NBLOK) layer or a nitrogen-doped silicon carbide (NDC) layer. Alternatively, the second dielectric layer 222 can have a selective Co cap over the metal lines 120, followed by the capping layer. The capping layer has a preferable thickness of about 20 nm. The capping layer is able to protect the metal lines 120 so that the conductive material is not exposed to the above dielectric layer. The first hardmask layer 226 is preferably an aluminum oxide (AlOx) layer with a thickness ranging from 2 to 10 nm. The second hardmask layer 240 is preferably a titanium nitride (TiN) layer with a thickness of about 30 nm.
As presented in the above detailed description, a metal shoulder is selectively grown on a seeding material and it provides a controllable aperture dimension for the interconnect via fabrication between metallization layers. A highly controlled atomic level deposition process is used to grow the metal shoulder to a precisely specified thickness. The aperture dimension of the via opening can then be precisely controlled by the width of the metal shoulder that is grown and this method can be used in different technology nodes in semiconductor device fabrication.
The terms “first”, “second”, “third”, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”.
While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.
