H. Jim Fulford Jr.

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for forming high performance three dimensionally stacked tr...
- Patent number 12,356,706
- Issue date Jul 8, 2025
- Tokyo Electron Limited
- H. Jim Fulford
Information Patent Grant
Epitaxial semiconductor 3D horizontal nano sheet with high mobility...
- Patent number 12,349,424
- Issue date Jul 1, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
Plurality of devices in adjacent 3D stacks in different circuit loc...
- Patent number 12,342,603
- Issue date Jun 24, 2025
- Tokyo Electron Limited
- H. Jim Fulford
Information Patent Grant
3D device with a plurality of core wiring layout architecture
- Patent number 12,342,568
- Issue date Jun 24, 2025
- Tokyo Electron Limited
- H. Jim Fulford
Information Patent Grant
High performance new channel materials precision aligned 3D CFET de...
- Patent number 12,336,270
- Issue date Jun 17, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D isolation of a segmentated 3D nanosheet channel region
- Patent number 12,328,919
- Issue date Jun 10, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of manufacturing thereof
- Patent number 12,324,206
- Issue date Jun 3, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
3D semiconductor device with 2D semiconductor material and method o...
- Patent number 12,317,577
- Issue date May 27, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
3D memory with cell stacking using an in-situ capacitor stack
- Patent number 12,317,481
- Issue date May 27, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
Semiconductor devices with crystallized channel regions and methods...
- Patent number 12,302,606
- Issue date May 13, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
Multi-dimensional metal first device layout and circuit design
- Patent number 12,288,747
- Issue date Apr 29, 2025
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D integration of 3D NAND and vertical logic beneath memory
- Patent number 12,289,885
- Issue date Apr 29, 2025
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
3D selective material transformation to integrate 2D material elements
- Patent number 12,272,692
- Issue date Apr 8, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Replacement channel 2D material integration
- Patent number 12,261,209
- Issue date Mar 25, 2025
- Tokyo Electron Limited
- Robert D. Clark
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
2D materials with inverted gate electrode for high density 3D stacking
- Patent number 12,249,659
- Issue date Mar 11, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form selective high-k deposition on 2D materials
- Patent number 12,243,920
- Issue date Mar 4, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor structures and methods utilizing selective form...
- Patent number 12,218,244
- Issue date Feb 4, 2025
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical semiconductor device in narrow slots within trench
- Patent number 12,218,195
- Issue date Feb 4, 2025
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making 3D segmented devices for enhanced 3D circuit density
- Patent number 12,218,011
- Issue date Feb 4, 2025
- Tokyo Electron Limited
- Mark Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of high density 3D circuits with enhanced 3D conductivity
- Patent number 12,191,210
- Issue date Jan 7, 2025
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D nano sheet method using 2D material integrated with conductive o...
- Patent number 12,176,249
- Issue date Dec 24, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional device with vertical core and bundled wiring
- Patent number 12,170,326
- Issue date Dec 17, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split substrate interposer with integrated passive device
- Patent number 12,148,687
- Issue date Nov 19, 2024
- Tokyo Electron Limited
- Arya Bhattacherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stackable semiconductor device with 2D material layer and methods o...
- Patent number 12,148,668
- Issue date Nov 19, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D memory with conductive dielectric channel integrated with logic...
- Patent number 12,133,387
- Issue date Oct 29, 2024
- Tokyo Electron Limited
- Mark I. Gardner
Information Patent Grant
Ultra dense 3D routing for compact 3D designs
- Patent number 12,131,956
- Issue date Oct 29, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making of plurality of 3D vertical logic elements integra...
- Patent number 12,114,480
- Issue date Oct 8, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance 3D vertical transistor device enhancement design
- Patent number 12,087,817
- Issue date Sep 10, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density logic formation using multi-dimensional laser annealing
- Patent number 12,087,640
- Issue date Sep 10, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D high density compact metal first approach for hybrid transistor...
- Patent number 12,068,205
- Issue date Aug 20, 2024
- Tokyo Electron Limited
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FORMATION OF HIGH DENSITY 3D CIRCUITS WITH ENHANCED 3D CONDUCTIVITY
- Publication number 20250120163
- Publication date Apr 10, 2025
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
Information Patent Application
3D COMB NANOSHEET AND PI/2 ROTATED NANOSHEET
- Publication number 20250081551
- Publication date Mar 6, 2025
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
Information Patent Application
3D SPACER NANOSHEET FORMATION
- Publication number 20250081552
- Publication date Mar 6, 2025
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT SUBSTRATE INTERPOSER WITH INTEGRATED PASSIVE DEVICE
- Publication number 20250046696
- Publication date Feb 6, 2025
- TOKYO ELECTRON LIMITED
- Arya BHATTACHERJEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA DENSE 3D ROUTING FOR COMPACT 3D DESIGNS
- Publication number 20250022756
- Publication date Jan 16, 2025
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES
- Publication number 20250015045
- Publication date Jan 9, 2025
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR TRANSISTOR MEMORY ELEMENT
- Publication number 20240341101
- Publication date Oct 10, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF 3D CANTILEVER CHANNEL FORMATION
- Publication number 20240304701
- Publication date Sep 12, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D U-SHAPED NANOSHEET DEVICE
- Publication number 20240282771
- Publication date Aug 22, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET
- Publication number 20240249978
- Publication date Jul 25, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE AND METHOD OF FORMING
- Publication number 20240243182
- Publication date Jul 18, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED NANOSHEET MEMORY ELEMENTS, DEVICES AND METHODS
- Publication number 20240215220
- Publication date Jun 27, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
Information Patent Application
THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM-POISEDON...
- Publication number 20240203797
- Publication date Jun 20, 2024
- TOKYO ELECTRON LIMITED
- Andrew WELOTH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240145595
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240145576
- Publication date May 2, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20240120407
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...
- Publication number 20240120336
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS
- Publication number 20240120375
- Publication date Apr 11, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES
- Publication number 20240113114
- Publication date Apr 4, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME
- Publication number 20240105777
- Publication date Mar 28, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE
- Publication number 20240096708
- Publication date Mar 21, 2024
- TOKYO ELECTRON LIMITED
- H. Jim FULFORD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS
- Publication number 20240079475
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS
- Publication number 20240079452
- Publication date Mar 7, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS
- Publication number 20240071871
- Publication date Feb 29, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063261
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION
- Publication number 20240063220
- Publication date Feb 22, 2024
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET
- Publication number 20230402505
- Publication date Dec 14, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...
- Publication number 20230378364
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230378366
- Publication date Nov 23, 2023
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
- Publication number 20230369505
- Publication date Nov 16, 2023
- TOKYO ELECTRON LIMITED
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS

H. Jim Fulford Jr.

Person

Patents Grantslast 30 patents

Methods for forming high performance three dimensionally stacked tr...

Epitaxial semiconductor 3D horizontal nano sheet with high mobility...

Plurality of devices in adjacent 3D stacks in different circuit loc...

3D device with a plurality of core wiring layout architecture

High performance new channel materials precision aligned 3D CFET de...

3D isolation of a segmentated 3D nanosheet channel region

Semiconductor devices and methods of manufacturing thereof

3D semiconductor device with 2D semiconductor material and method o...

3D memory with cell stacking using an in-situ capacitor stack

Semiconductor devices with crystallized channel regions and methods...

Multi-dimensional metal first device layout and circuit design

3D integration of 3D NAND and vertical logic beneath memory

3D selective material transformation to integrate 2D material elements

Replacement channel 2D material integration

2D materials with inverted gate electrode for high density 3D stacking

Method to form selective high-k deposition on 2D materials

Vertical transistor structures and methods utilizing selective form...

Vertical semiconductor device in narrow slots within trench

Method of making 3D segmented devices for enhanced 3D circuit density

Formation of high density 3D circuits with enhanced 3D conductivity

3D nano sheet method using 2D material integrated with conductive o...

Three-dimensional device with vertical core and bundled wiring

Split substrate interposer with integrated passive device

Stackable semiconductor device with 2D material layer and methods o...

3D memory with conductive dielectric channel integrated with logic...

Ultra dense 3D routing for compact 3D designs

Method of making of plurality of 3D vertical logic elements integra...

High performance 3D vertical transistor device enhancement design

High density logic formation using multi-dimensional laser annealing

3D high density compact metal first approach for hybrid transistor...

Patents Applicationslast 30 patents

FORMATION OF HIGH DENSITY 3D CIRCUITS WITH ENHANCED 3D CONDUCTIVITY

3D COMB NANOSHEET AND PI/2 ROTATED NANOSHEET

3D SPACER NANOSHEET FORMATION

SPLIT SUBSTRATE INTERPOSER WITH INTEGRATED PASSIVE DEVICE

ULTRA DENSE 3D ROUTING FOR COMPACT 3D DESIGNS

METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES

SEMICONDUCTOR DEVICE AND METHOD FOR TRANSISTOR MEMORY ELEMENT

METHOD OF 3D CANTILEVER CHANNEL FORMATION

3D U-SHAPED NANOSHEET DEVICE

DEVICE AND METHOD OF FORMING 3D U-SHAPED NANOSHEET CFET

MICROELECTRONIC DEVICE AND METHOD OF FORMING

INTEGRATED NANOSHEET MEMORY ELEMENTS, DEVICES AND METHODS

THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM-POISEDON...

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

3D NANOSHEET STACK WITH DUAL SELECTIVE CHANNEL REMOVAL OF HIGH MOBI...

HIGH PERFORMANCE 3D CHANNELS WITH UPSILON NANOSHEETS

METHODS FOR FORMING HIGH PERFORMANCE 3D NANO SHEET DEVICES

3D UFET DEVICES AND METHODS FOR MANUFACTURING THE SAME

HIGH PERFORMANCE 3D COMPACT TRANSISTOR ARCHITECTURE

METHODS OF COMPACT CELL DESIGN FOR LOGIC APPLICATIONS

VERTICAL TRANSISTOR STRUCTURES WITH OFFSET SPACERS

3D HIGH DENSITY DEVICES INTEGRATED WITH SOURCE AND DRAIN RAILS

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

3D ISOLATION OF A SEGMENTATED 3D NANOSHEET CHANNEL REGION

HIGH DENSITY 3D TRANSPORT DEVICE NANO SHEET

3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTO...

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME