Patent Application
20240079452
This disclosure relates to microelectronic devices including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.
In the manufacture of semiconductor devices (especially on the microscopic scale), various fabrication processes are executed, for example, film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments, among others. These processes can be performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring or metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.
One aspect of the present disclosure is directed to a transistor structure. The structure includes a substrate including a first region and a second region. The structure includes a first lower metal layer and a first upper metal layer in the first region, wherein the first lower metal layer and the first upper metal layer are spaced from each other with a first isolation material. The structure includes a first channel extending from the first lower metal layer to the first upper metal layer. The structure includes a first gate electrode surrounded by the first channel and vertically spaced from each of the first lower metal layer and the first upper metal layer. The structure includes a second lower metal layer and a second upper metal layer in second region, wherein the second lower metal layer and the second upper metal layer are spaced from each other with a second isolation material. The structure includes a second channel extending from the second lower metal layer to the second upper metal layer. The structure includes a second gate electrode surrounded by the second channel and vertically spaced from each of the second lower metal layer and the second upper metal layer.
The structure further includes a first dielectric spacer disposed below the first gate electrode; a second dielectric spacer disposed above the first gate electrode; a third dielectric spacer disposed below the second gate electrode; and a fourth dielectric spacer disposed above the second gate electrode. The first and second dielectric spacers are each surrounded by the first channel, and the third and fourth dielectric spacers are each surrounded by the second channel. The first dielectric spacer elevates a bottom surface of the first gate electrode away from the first lower metal layer, and the second dielectric spacer lowers a top surface of the first gate electrode away from the first upper metal layer. The third dielectric spacer elevates a bottom surface of the second gate electrode away from the second lower metal layer, and the fourth dielectric spacer lowers a top surface of the second gate electrode away from the second upper metal layer.
The first gate electrode has a first conductive type, and the second gate electrode has a second conductive type.
The structure further includes a first gate dielectric extending from the first lower metal layer to the first upper metal layer, and surrounded by the first channel; and a second gate dielectric extending from the second lower metal layer to the second upper metal layer, and surrounded by the second channel.
The first channel includes at least one of: indium oxide (In2O3), tin dioxide (SnO2), zinc oxide (ZnO), or InGaZnO, and the second channel includes tin oxide (SnO)
The structure further includes a first via structure extending through the first upper metal layer and the first isolation material, and in electrical contact with the first lower metal layer; a second via structure extending through a dielectric spacer disposed above the first gate electrode, and in electrical contact with the first gate electrode; a third via structure in electrical contact with the first upper metal layer; a fourth via structure extending through the second upper metal layer and the second isolation material, and in electrical contact with the second lower metal layer; a fifth via structure extending through a dielectric spacer disposed above the second gate electrode, and in electrical contact with the second gate electrode; and a sixth via structure in electrical contact with the second upper metal layer.
Another aspect of the present disclosure is directed to a transistor structure. The structure includes a first lower metal layer extending along one or more lateral directions. The structure includes a first upper metal layer in parallel with the first lower metal layer, wherein the first lower metal layer and the first upper metal layer are spaced from each other with a first isolation material. The structure includes a first channel extending from the first lower metal layer to the first upper metal layer. The structure includes a first dielectric spacer surrounded by the first channel and further by the first lower metal layer. The structure includes a second dielectric spacer also surrounded by the first channel and further by the first upper metal layer. The structure includes a first gate electrode surrounded by the first channel and vertically interposed between the first dielectric spacer and the second dielectric spacer.
The first dielectric spacer elevates a bottom surface of the first gate electrode away from the first lower metal layer, and the second dielectric spacer lowers a top surface of the first gate electrode away from the first upper metal layer.
The structure further includes a first gate dielectric extending from the first lower metal layer to the first upper metal layer, and interposed between the first channel and a combination of the first dielectric spacer, the first gate electrode, and the second dielectric spacer.
The structure further includes a second lower metal layer extending along the one or more lateral directions; a second upper metal layer in parallel with the second lower metal layer, wherein the second lower metal layer and the second upper metal layer are spaced from each other with a second isolation material; a second channel extending from the second lower metal layer to the second upper metal layer; a third dielectric spacer surrounded by the second channel and further by the second lower metal layer; a fourth dielectric spacer also surrounded by the second channel and further by the second upper metal layer; and a second gate electrode surrounded by the second channel and vertically interposed between the third dielectric spacer and the fourth dielectric spacer. The first gate electrode has a first conductive type, and the second gate electrode has a second conductive type.
The structure further includes a third lower metal layer extending along the one or more lateral directions; a third upper metal layer in parallel with the third lower metal layer, wherein the third lower metal layer and the third upper metal layer are spaced from each other with a third isolation material; a third channel extending from the third lower metal layer to the third upper metal layer; a fifth dielectric spacer surrounded by the third channel and further by the third lower metal layer; a sixth dielectric spacer also surrounded by the third channel and further by the third upper metal layer; and a third gate electrode surrounded by the third channel and vertically interposed between the fifth dielectric spacer and the sixth dielectric spacer. The first gate electrode and the third gate electrode have an identical conductive type.
The first lower metal layer and the third lower metal layer are formed as a first one-piece structure, and the first upper metal layer and the third upper metal layer are formed as a second one-piece structure. The first lower metal layer and the third lower metal layer are isolated from each other, and the first upper metal layer and the third upper metal layer are isolated from each other.
Yet another aspect of the present disclosure is directed to a method for forming a transistor structure. The method includes forming a stack including a lower metal layer, an isolation material, and an upper metal layer, wherein the lower metal layer and the upper metal layer are spaced from each other with the isolation material. The method includes forming a first opening extending through the stack. The method includes lining an inner sidewall of the first opening with a first channel. The method includes sequentially forming a first dielectric spacer, a first gate electrode, and a second dielectric spacer in the first opening, wherein a combination of the first dielectric spacer, the first gate electrode, and the second dielectric spacer is surrounded by the first channel.
The first dielectric spacer elevates a bottom surface of the gate electrode away from the lower metal layer, and the second dielectric spacer lowers a top surface of the gate electrode away from the upper metal layer.
The method further includes forming a second opening extending through the stack; lining an inner sidewall of the second opening with a second channel; and sequentially forming a third dielectric spacer, a second gate electrode, and a fourth dielectric spacer in the second opening, wherein a combination of the third dielectric spacer, the second gate electrode, and the fourth dielectric spacer is surrounded by the second channel.
These and other aspects and implementations are discussed in detail below. The foregoing information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and character of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of the various aspects and implementations, and are incorporated in and constitute a part of this specification. Aspects can be combined, and it will be readily appreciated that features described in the context of one aspect of the invention can be combined with other aspects. Aspects can be implemented in any convenient form. As used in the specification and in the claims, the singular form of “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.
Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying figures, which are schematic and are not intended to be drawn to scale. Unless indicated as representing the background art, the figures represent aspects of the disclosure. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:
Disclosed herein are embodiments related to one or more transistor structures having a central vertical metal structure. In some embodiments, the vertical metal structure may occupy an innermost level of an opening forming a transistor structure and operatively function as the gate of said transistor structure. Based on such a vertical metal structure, advantageously, the transistor structures, as disclosed herein, may be formed as channel-all-around (CAA) or channel around gate (CAG) transistor structures, where a channel layer may wrap around this vertical metal gate structure. Based on such transistor structures, any number of the disclosed vertical metal structures can be laterally (e.g., side-by-side) arranged with each other and/or vertically stacked on top of one another, thereby forming an array of transistor structures having improved characteristics in an area efficient manner. In various embodiments, an arrangement of the channel layer formed around the metal structures can be flexibly configured. For example, the channel layer can have a single material (e.g., a conductive oxide material) or plural materials (e.g., a conductive oxide material wrapping around a two-dimensional (2D) material). In general, conductive oxide materials/2D materials can allow significant boost in performance relative to silicon (Si), such that transistor structures disclosed herein may have improved performances or characteristics (e.g., improved transconductance (gm), improved gain bandwidth (Ft), improved saturation current (Idsat), etc.).
Reference will now be made to the illustrative embodiments depicted in the drawings, and specific language will be used here to describe the same. It will nevertheless be understood that no limitation of the scope of the claims or this disclosure is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the subject matter disclosed herein. Other embodiments may be used and/or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to be limiting of the subject matter presented.
Likewise, although the Figures and aspects of the disclosure may show or describe devices herein as having a particular shape, it should be understood that such shapes are merely illustrative and should not be considered limiting to the scope of the techniques described herein. For example, although certain figures show various layers defining transistor structures or other electric structures in a circular configuration, other shapes are also contemplated, and indeed the techniques described herein may be implemented in any shape or geometry.
In various embodiments, operations of the method 100 may be associated with top views or cross-sectional views of an example semiconductor device 200 at various fabrication stages as shown in
In brief overview, the method 100 starts with operation 102 of forming a stack of layers including a lower metal layer, an isolation material, and an upper metal layer. The method 100 continues to operation 104 of forming a first opening through the stack. The method 100 proceeds to operation 106 of lining the first opening first with a first channel layer and then with a first gate dielectric layer. The method 100 proceeds to operation 108 of forming a first dielectric spacer in the first opening. The method 100 proceeds to operation 110 of forming a first gate electrode in the first opening. The method 100 proceeds to operation 112 of forming a second dielectric spacer in the first opening. In various embodiments, the first gate electrode is vertically interposed between the first and second dielectric spacers, with the first channel layer wrapping around a combination of the first dielectric spacer, first gate electrode, and second dielectric spacer. The method 100 proceeds to operation 114 of forming a second opening through the stack. The method 100 proceeds to operation 116 of lining the second opening first with a second channel layer and then with a second gate dielectric layer. The method 100 proceeds to operation 118 of forming a third dielectric spacer in the second opening. The method 100 proceeds to operation 120 of forming a second gate electrode in the second opening. The method 100 proceeds to operation 122 of forming a fourth dielectric spacer in the second opening. In various embodiments, the second gate electrode is vertically interposed between the third and fourth dielectric spacers, with the second channel layer wrapping around a combination of the third dielectric spacer, second gate electrode, and fourth dielectric spacer. In various embodiments, upon operation 122 being performed, a first vertical transistor and a second vertical transistor can be formed in the first opening and the second opening, respectively. The method 100 proceeds to operation 124 of isolating the first vertical transistor and the second vertical transistor. The method 100 proceeds to operation 126 of forming a respective number of contact structures for each of the first vertical transistor and the second vertical transistor.
Corresponding to operation 102 of
As shown, prior to forming the stack 210, a dielectric layer 204 is formed over the substrate 202. In some embodiments, the dielectric layer 204 (e.g., including silicon nitride) may serve as an etch stop layer when etching the stack 210. The stack 210 can include a lower metal layer 212, an isolation material 214 over the lower metal layer 212, and an upper metal layer 216 over the isolation material 214. As such, the lower metal layer 212 and the upper metal layer 216 may be electrically isolated from each other by the isolation material 214. Further, each of the lower metal layer 212, the isolation material 214, and the upper metal layer 216 may extend over the substrate 202 in multiple lateral directions.
The substrate 202 may be any semiconductor, insulator or conductor. In some embodiments, the substrate 202 comprises a semiconductor material such as silicon or germanium. The substrate 202 may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate 202 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate 202 includes an epitaxial layer. For example, the substrate 202 may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate 202 may include a semiconductor-on-insulator (SOI) structure. For example, the substrate 202 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.
In various embodiments, the lower metal layer 212 may be first formed (e.g., deposited) over the substrate 202, followed by the formation (e.g., deposition) of the isolation material 214 and then the upper metal layer 216. The metal layers 212 and 216, which may later be patterned as source and drain electrodes of one or more vertical transistors, may have a same metal material. The metal material may include copper, aluminum, or the like. The metal material may be deposited by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable metal filling process. The isolation material 214 may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other isolation materials and/or other formation processes may be used. An anneal process may be performed once the isolation material is formed.
Corresponding to operation 104 of
Upon forming the stack 210, a patternable layer (e.g., a photoresist mask) 304 including one or more patterns can be formed thereupon. Next, following the patterns, an etching process (e.g., an anisotropic etching process) is performed to etch respective portions of the lower metal layer 212, the isolation material 214, and the upper metal layer 216, thereby forming the first opening 302. In some embodiments, the etching process can be stopped by the dielectric layer 204. As such, the first opening 302 can extend through the upper metal layer 216, the isolation material 214, and the lower metal layer 212. Alternatively stated, upon the first opening 302 is formed, respective inner sidewalls of the upper metal layer 216, the isolation material 214, and the lower metal layer 212 can be exposed. As will be shown in the top view of the semiconductor device 200 below, the first opening 302 can be formed with a circular shape. However, it should be understood that the first opening 302 can be formed in any of various shapes, while remaining within the scope of the present disclosure.
Corresponding to operation 106 of
As shown in
In some embodiments, the first channel layer 402 includes one or more semiconductive-behaving materials (e.g., conductive oxide materials), which may be formed using certain elements that, when combined with oxygen, form a new material that exhibits semiconductive behavior. For example, the semiconductive behaving material can be “turned off” and can have a low or practically no off-state leakage current, and the semiconductive behaving material can be “turned on” and become highly conductive when voltage is applied. Example materials to create an n-type channel for example include, but are not limited to, In2O3, SnO2, In GaZnO, and ZnO. Example materials that can be used to create a p-type channel may be formed utilizing, for example, SnO. These materials may be further doped to improve the electrical characteristics. These materials may also be referred to as conductive oxides or semiconductive behaving oxides for the purposes of this discussion. In one aspect of the present disclosure, the first channel layer 402 may be configured as a p-type channel.
The first gate dielectric layer 404 may be formed of a single high-k dielectric material, multiple different high-k dielectric materials, or multiple similar high-k dielectric materials. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The first gate dielectric layer 404 can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the first gate dielectric layer 404 may optionally include a substantially thin oxide (e.g., SiOx) layer.
Corresponding to operation 108 of
The first dielectric spacer 602 may be formed in the first opening 302 with a first height (H1), thereby occupying a first portion of the first opening 302. The first dielectric spacer 602 may have an isolation material. The isolation material of the first dielectric spacer 602 may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other isolation materials and/or other formation processes may be used.
Corresponding to operation 110 of
The first gate electrode 702 may be formed in the first opening 302 with a second height (H2), thereby occupying a second portion of the first opening 302. The first gate electrode 702 is formed over the first dielectric spacer 602, and thus, a bottom surface of the first gate electrode 702 is in contact with a top surface of the first dielectric spacer 602. The first gate electrode 702 may include a metal material. The metal material may include a work function metal that is configured to form, at least in part, the gate of a corresponding vertical transistor. For example, the first gate electrode 702 may include one or more p-type work function metals. Example p-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The work function metal(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
Corresponding to operation 112 of
The second dielectric spacer 902 may be formed in the first opening 302 with a third height (H3), thereby occupying a third portion of the first opening 302. The second dielectric spacer 902 may have an isolation material. The isolation material of the second dielectric spacer 902 may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other isolation materials and/or other formation processes may be used.
The second dielectric spacer 902 is formed over the first gate electrode 702, and thus, a top surface of the first gate electrode 702 is in contact with a bottom surface of the second dielectric spacer 902. After forming the second dielectric spacer 902, the first channel layer 402 can surround a combination of the second dielectric spacer 902, the first gate electrode 702, and the first dielectric spacer 602, with a central portion of the first channel layer 402 wrapping around the first gate electrode 702. In various embodiments, the first dielectric spacer 602 is configured to vertically elevate the first gate electrode 702 from the lower metal layer 212 (e.g., to reduce capacitance coupled between the gate and one of the source or drain of a corresponding vertical transistor), and the second dielectric spacer 902 is configured to vertically lower the first gate electrode 702 from the upper metal layer 216 (e.g., to reduce capacitance coupled between the gate and the other source or drain of the corresponding vertical transistor).
Corresponding to operation 114 of
Upon forming the second dielectric spacer 902, a patternable layer (e.g., a photoresist mask) 1104 including one or more patterns can be formed on a dielectric layer 1103. Next, following the patterns, an etching process (e.g., an anisotropic etching process) is performed to etch respective portions of the lower metal layer 212, the isolation material 214, and the upper metal layer 216, thereby forming the second opening 1102. In some embodiments, the etching process can be stopped by the dielectric layer 204. As such, the second opening 1102 can extend through the upper metal layer 216, the isolation material 214, and the lower metal layer 212. Alternatively stated, upon the second opening 1102 is formed, respective inner sidewalls of the upper metal layer 216, the isolation material 214, and the lower metal layer 212 can be exposed. Similarly, the second opening 1102 can be formed with a circular shape. However, it should be understood that the second opening 1102 can be formed in any of various shapes, while remaining within the scope of the present disclosure.
In various embodiments, following operation 114, the method 100 continues to operation 116, 118, 120, 122, which are substantially similar to operations 106, 108, 110, and 112, respectively, except that a second channel layer is configured as an n-type channel and a second gate electrode with a second, different conductive type (n-type) is formed in the second opening 802.
For example in a cross-sectional view of the semiconductor device 200 in
Corresponding to operation 124 of
As shown in
To form these source and drain electrodes, a patternable layer (e.g., a photoresist mask) 1404 including one or more patterns can be formed on a dielectric layer 1403. Next, following the patterns, an etching process (e.g., an anisotropic etching process) is performed to etch respective portions of the lower metal layer 212, the isolation material 214, and the upper metal layer 216, thereby isolating the source and drain electrodes of each first/second transistor from the source and drain electrodes of another first/second transistor. Specifically, with the etching process, a number of openings 1402 that extend through the stack 210 can be formed, which expose corresponding portions of the dielectric layer 204, respectively. The openings 1402 can then be filled with an isolation material 1602 (e.g., silicon oxide, silicon nitride, the like, or combinations thereof) and this isolation material 1602 can further overlay the workpiece with a certain thickness, as shown in a cross-sectional view of the semiconductor device 200 in
Corresponding to operation 126 of
Each of the contact structures 1710S, 1710G, 1710D, 1760S, 1760G, and 1760D is formed as a via structure that extends through one or more materials to be in contact with a respective conductive feature. For example, the contact structures 1710S and 1760S can each extend through the isolation material 214 to be in contact with the lower metal layer 211 of a corresponding transistor (functioning as its source electrode); the contact structures 1710D and 1760D can each extend through the isolation material 1602 to be in contact with the upper metal layer 216 of a corresponding transistor (functioning as its drain electrode); and the contact structures 1710G and 1760G can each extend through the isolation material 1602 and the corresponding dielectric spacer to be in contact with the gate electrode of a corresponding transistor.
Each of the contact structures 1710S, 1710G, 1710D, 1760S, 1760G, and 1760D includes at least one metal material. The metal material may include copper, aluminum, or the like. The metal material may be deposited by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), and/or other suitable metal filling process in a damascene process to form the contact structure. Further, at least some of the contact structures 1710S, 1710G, 1710D, 1760S, 1760G, and 1760D can each be surrounded by a dielectric material (e.g., 1720) to electrically isolate the contact structure from adjacent conductive feature(s), in some embodiments.
Based on the transistor structure discussed above, a number of transistors, with either the same conductive type or different conductive types, can be vertically stacked on top of one another. For example,
In another example,
In some other embodiments, a plural number of transistors can share a respective pair of source electrode and drain electrode. For example,
Based on the configuration shown in
In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.
