Habeeb Farah

Person

Nazareth, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for assertion-based formal verification using uni...
- Patent number 11,520,964
- Issue date Dec 6, 2022
- Cadence Design Systems, Inc.
- Ahmad S. Abo Foul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for assertion-based formal verification using cac...
- Patent number 11,514,219
- Issue date Nov 29, 2022
- Cadence Design Systems, Inc.
- Ahmad S. Abo Foul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for formal bug hunting
- Patent number 11,080,448
- Issue date Aug 3, 2021
- Cadence Design Systems, Inc.
- Yaron Schiller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequential equivalence checking
- Patent number 11,023,357
- Issue date Jun 1, 2021
- Cadence Design Systems, Inc.
- Ayman Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for sequential equival...
- Patent number 10,984,161
- Issue date Apr 20, 2021
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for automatically infe...
- Patent number 10,983,758
- Issue date Apr 20, 2021
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequential equivalence checking
- Patent number 10,853,546
- Issue date Dec 1, 2020
- Cadence Design Systems, Inc.
- Yaron Schiller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for generating a forma...
- Patent number 10,789,404
- Issue date Sep 29, 2020
- Cadence Design Systems, Inc.
- Rajdeep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for clock gating in a...
- Patent number 10,782,767
- Issue date Sep 22, 2020
- Cadence Design Systems, Inc.
- Karam Abd Elkader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for improving coverage...
- Patent number 10,546,083
- Issue date Jan 28, 2020
- Cadence Design Systems, Inc.
- Amit Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for filtering one or m...
- Patent number 10,452,798
- Issue date Oct 22, 2019
- Cadence Design Systems, Inc.
- Nizar Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics for circuit design properties
- Patent number 9,177,089
- Issue date Nov 3, 2015
- Cadence Design Systems, Inc.
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics of covered events for circuit...
- Patent number 9,158,874
- Issue date Oct 13, 2015
- Cadence Design Systems, Inc.
- Rajeev K. Ranjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification coverage metrics for circuit design properties
- Patent number 8,826,201
- Issue date Sep 2, 2014
- Jasper Design Automation, Inc.
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic design development tool and method
- Patent number 7,346,864
- Issue date Mar 18, 2008
- Intel Corporation
- Johny Srouji
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES
- Publication number 20150135150
- Publication date May 14, 2015
- Ziyad E. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic design development tool and method
- Publication number 20060229859
- Publication date Oct 12, 2006
- Intel Corporation
- Johny Srouji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system and apparatus for quotient digit generation
- Publication number 20060224657
- Publication date Oct 5, 2006
- Intel Corporation
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING

Habeeb Farah

Person

Patents Grantslast 30 patents

Method and system for assertion-based formal verification using uni...

System and method for assertion-based formal verification using cac...

Method and system for formal bug hunting

Method and system for sequential equivalence checking

System, method, and computer program product for sequential equival...

System, method, and computer program product for automatically infe...

Method and system for sequential equivalence checking

System, method, and computer program product for generating a forma...

System, method, and computer program product for clock gating in a...

System, method, and computer program product for improving coverage...

System, method, and computer program product for filtering one or m...

Formal verification coverage metrics for circuit design properties

Formal verification coverage metrics of covered events for circuit...

Formal verification coverage metrics for circuit design properties

Logic design development tool and method

Patents Applicationslast 30 patents

FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES

Logic design development tool and method

Method, system and apparatus for quotient digit generation