Han-Pin Chung

Person

Fongshan City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming semiconductor structure with high aspect ratio
- Patent number 11,823,960
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 10,872,961
- Issue date Dec 22, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming semiconductor structure with high aspect ratio
- Patent number 10,840,154
- Issue date Nov 17, 2020
- Taiwan Semiconductor Manufacturing Co. LTD
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device structure and method for enlarging gap-fill window
- Patent number 10,629,497
- Issue date Apr 21, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doping for FinFET
- Patent number 9,659,776
- Issue date May 23, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Kai Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doping for FinFET
- Patent number 9,362,404
- Issue date Jun 7, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Kai Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall free CESL for enlarging ILD gap-fill window
- Patent number 9,218,974
- Issue date Dec 22, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Sidewall-free CESL for enlarging ILD gap-fill window
- Patent number 8,999,834
- Issue date Apr 7, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of dual epi process for semiconductor device
- Patent number 8,900,957
- Issue date Dec 2, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of dual EPI process for semiconductor device
- Patent number 8,900,956
- Issue date Dec 2, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of dual EPI process for semiconductor device
- Patent number 8,609,497
- Issue date Dec 17, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating gate electrode using a treated hard mask
- Patent number 8,569,185
- Issue date Oct 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Matt Yeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
STI structure and method of forming bottom void in same
- Patent number 8,461,015
- Issue date Jun 11, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Lien Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure with multiple spacers
- Patent number 8,299,508
- Issue date Oct 30, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor Chiuan Hsieh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO
- Publication number 20240047276
- Publication date Feb 8, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Thereof
- Publication number 20210233764
- Publication date Jul 29, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO
- Publication number 20210043523
- Publication date Feb 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20200052081
- Publication date Feb 13, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Han-Pin CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO
- Publication number 20190164848
- Publication date May 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Han-Pin CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET DEVICE STRUCTURE AND METHOD FOR ENLARGING GAP-FILL WINDOW
- Publication number 20190131186
- Publication date May 2, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Han-Pin CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Doping for FinFET
- Publication number 20160260610
- Publication date Sep 8, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Kai Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Doping for FinFET
- Publication number 20150243739
- Publication date Aug 27, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Kai Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWALL-FREE CESL FOR ENLARGING ILD GAP-FILL WINDOW
- Publication number 20140170846
- Publication date Jun 19, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF DUAL EPI PROCESS FOR SEMICONDCUTOR DEVICE
- Publication number 20140073097
- Publication date Mar 13, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF DUAL EPI PROCESS FOR SEMICONDUCTOR DEVICE
- Publication number 20140073096
- Publication date Mar 13, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sidewall-Free CESL for Enlarging ILD Gap-Fill Window
- Publication number 20130270651
- Publication date Oct 17, 2013
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal Leveling for Semiconductor Devices
- Publication number 20120015459
- Publication date Jan 19, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chun Hsiung Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Dual EPI Process For Semiconductor Device
- Publication number 20110201164
- Publication date Aug 18, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK
- Publication number 20110195548
- Publication date Aug 11, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Matt Yeh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS STRUCTURE WITH MULTIPLE SPACERS
- Publication number 20110031538
- Publication date Feb 10, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor Chiuan HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME
- Publication number 20110006390
- Publication date Jan 13, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Lien HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sidewall-Free CESL for Enlarging ILD Gap-Fill Window
- Publication number 20100314690
- Publication date Dec 16, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Han-Pin Chung
- H01 - BASIC ELECTRIC ELEMENTS

Han-Pin Chung

Person

Patents Grantslast 30 patents

Method for forming semiconductor structure with high aspect ratio

Semiconductor device and manufacturing method thereof

Method for forming semiconductor structure with high aspect ratio

FinFET device structure and method for enlarging gap-fill window

Doping for FinFET

Doping for FinFET

Sidewall free CESL for enlarging ILD gap-fill window

Sidewall-free CESL for enlarging ILD gap-fill window

Method of dual epi process for semiconductor device

Method of dual EPI process for semiconductor device

Method of dual EPI process for semiconductor device

Method of fabricating gate electrode using a treated hard mask

STI structure and method of forming bottom void in same

CMOS structure with multiple spacers

Patents Applicationslast 30 patents

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO

Semiconductor Device and Method of Forming Thereof

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO

FINFET DEVICE STRUCTURE AND METHOD FOR ENLARGING GAP-FILL WINDOW

Doping for FinFET

Doping for FinFET

SIDEWALL-FREE CESL FOR ENLARGING ILD GAP-FILL WINDOW

METHOD OF DUAL EPI PROCESS FOR SEMICONDCUTOR DEVICE

METHOD OF DUAL EPI PROCESS FOR SEMICONDUCTOR DEVICE

Sidewall-Free CESL for Enlarging ILD Gap-Fill Window

Thermal Leveling for Semiconductor Devices

Method of Dual EPI Process For Semiconductor Device

METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK

CMOS STRUCTURE WITH MULTIPLE SPACERS

STI STRUCTURE AND METHOD OF FORMING BOTTOM VOID IN SAME

Sidewall-Free CESL for Enlarging ILD Gap-Fill Window