HariKrishna CHINTARLAPALLI REDDY

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Bias current receiver with selective coupling circuit
- Patent number 12,057,829
- Issue date Aug 6, 2024
- QUALCOMM Incorporated
- Abhinav Murali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bias current receiver with selective coupling circuit
- Patent number 11,736,105
- Issue date Aug 22, 2023
- QUALCOMM Incorporated
- Abhinav Murali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Thin-film resistors with flexible terminal placement for area saving
- Patent number 11,424,054
- Issue date Aug 23, 2022
- QUALCOMM Incorporated
- Harikrishna Chintarlapalli Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin-film resistors with flexible terminal placement for area saving
- Patent number 11,056,253
- Issue date Jul 6, 2021
- QUALCOMM Incorporated
- Harikrishna Chintarlapalli Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Analog-mixed signal circuit cells with universal Fin pitch and poly...
- Patent number 10,978,437
- Issue date Apr 13, 2021
- QUALCOMM Incorporated
- Jonathan Holland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cell architecture with intrinsic decoupling capacitor
- Patent number 10,163,884
- Issue date Dec 25, 2018
- QUALCOMM Incorporated
- Harikrishna Chintarlapalli Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stacked common gate finFET devices for area optimization
- Patent number 9,397,101
- Issue date Jul 19, 2016
- QUALCOMM Incorporated
- HariKrishna Chintarlapalli Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Length-of-diffusion protected circuit and method of design
- Patent number 9,093,995
- Issue date Jul 28, 2015
- QUALCOMM Incorporated
- Kashyap Ramachandra Bellur
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
BIAS CURRENT RECEIVER WITH SELECTIVE COUPLING CIRCUIT
- Publication number 20230396248
- Publication date Dec 7, 2023
- QUALCOMM Incorporated
- Abhinav MURALI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CELL ARCHITECTURE WITH AN ADDITIONAL OXIDE DIFFUSION REGION
- Publication number 20220181325
- Publication date Jun 9, 2022
- QUALCOMM Incorporated
- Harikrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING
- Publication number 20210287829
- Publication date Sep 16, 2021
- QUALCOMM Incorporated
- Harikrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANALOG-MIXED SIGNAL CIRCUIT CELLS WITH UNIVERSAL FIN PITCH AND POLY...
- Publication number 20200411500
- Publication date Dec 31, 2020
- QUALCOMM Incorporated
- Jonathan HOLLAND
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING
- Publication number 20200303094
- Publication date Sep 24, 2020
- QUALCOMM Incorporated
- Harikrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE PATTERNED STACKING TECHNIQUE
- Publication number 20150287709
- Publication date Oct 8, 2015
- QUALCOMM Incorporated
- HariKrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION
- Publication number 20150255461
- Publication date Sep 10, 2015
- QUALCOMM Incorporated
- HariKrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN
- Publication number 20140354338
- Publication date Dec 4, 2014
- Kashyap Ramachandra Bellur
- G06 - COMPUTING CALCULATING COUNTING

HariKrishna CHINTARLAPALLI REDDY

Person

Patents Grantslast 30 patents

Bias current receiver with selective coupling circuit

Bias current receiver with selective coupling circuit

Thin-film resistors with flexible terminal placement for area saving

Thin-film resistors with flexible terminal placement for area saving

Analog-mixed signal circuit cells with universal Fin pitch and poly...

Cell architecture with intrinsic decoupling capacitor

Stacked common gate finFET devices for area optimization

Length-of-diffusion protected circuit and method of design

Patents Applicationslast 30 patents

BIAS CURRENT RECEIVER WITH SELECTIVE COUPLING CIRCUIT

CELL ARCHITECTURE WITH AN ADDITIONAL OXIDE DIFFUSION REGION

THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING

ANALOG-MIXED SIGNAL CIRCUIT CELLS WITH UNIVERSAL FIN PITCH AND POLY...

THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING

DOUBLE PATTERNED STACKING TECHNIQUE

STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION

LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN