Harsaran S. Bhatia

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable random logic arrays using PN isolation
- Patent number 7,704,802
- Issue date Apr 27, 2010
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent sensor network
- Patent number 7,701,874
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Eric V. Kline
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable random logic arrays using PN isolation
- Patent number 7,420,248
- Issue date Sep 2, 2008
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested design approach
- Patent number 7,325,213
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded inductor and method of making
- Patent number 6,975,199
- Issue date Dec 13, 2005
- International Business Machines Corporation
- David Clifford Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a dielectric substrate having a multiturn inductor
- Patent number 6,931,712
- Issue date Aug 23, 2005
- International Business Machines Corporation
- David Clifford Long
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
MLC frequency selective circuit structures
- Patent number 6,806,793
- Issue date Oct 19, 2004
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and circuit for electrical testing of isolation resistance o...
- Patent number 6,573,728
- Issue date Jun 3, 2003
- International Business Machines Corporation
- Harsaran S. Bhatia
- G01 - MEASURING TESTING
Information Patent Grant
Substrate design of a chip using a generic substrate design
- Patent number 6,528,735
- Issue date Mar 4, 2003
- International Business Machines Corporation
- Harsaran S. Bhatia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Corrosion-free multi-layer conductor
- Patent number 6,203,926
- Issue date Mar 20, 2001
- International Business Machines Corporation
- Umar Moez Uddin Ahmad
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for corrosion free multi-layer metal conductors
- Patent number 5,427,983
- Issue date Jun 27, 1995
- International Business Machines Corporation
- Umar M. U. Ahmad
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Direct distribution repair and engineering change system
- Patent number 5,243,140
- Issue date Sep 7, 1993
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky diode having limited area self-aligned guard ring and meth...
- Patent number 4,796,069
- Issue date Jan 3, 1989
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic EC for minimizing EC pads
- Patent number 4,746,815
- Issue date May 24, 1988
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dotting circuit with inhibit function
- Patent number 4,743,781
- Issue date May 10, 1988
- International Business Machines Corporation
- Harsaran S. Bhatia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure for contacting a narrow width PN junction region
- Patent number 4,712,125
- Issue date Dec 8, 1987
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making Schottky diode having limited area self-aligned g...
- Patent number 4,691,435
- Issue date Sep 8, 1987
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and resulting structure for selective multiple base width tr...
- Patent number 4,535,531
- Issue date Aug 20, 1985
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for contacting a narrow width PN junction region
- Patent number 4,507,171
- Issue date Mar 26, 1985
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making high sheet resistivity resistors
- Patent number 4,464,212
- Issue date Aug 7, 1984
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density memory cell
- Patent number 4,427,989
- Issue date Jan 24, 1984
- International Business Machines Corporation
- Narasipur G. Anantha
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell resistor device
- Patent number 4,426,655
- Issue date Jan 17, 1984
- International Business Machines Corporation
- Harsaran S. Bhatia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of planarizing silicon dioxide in semiconductor devices
- Patent number 4,389,281
- Issue date Jun 21, 1983
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for avoiding residue on a vertical walled mesa
- Patent number 4,389,294
- Issue date Jun 21, 1983
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making stable nitride-defined Schottky barrier diodes
- Patent number T101201
- Issue date Nov 3, 1981
- Narasipur G. Anantha
- 156 - Adhesive bonding and miscellaneous chemical manufacture
Information Patent Grant
Method for making a lateral PNP or NPN with a high gain utilizing r...
- Patent number 4,264,382
- Issue date Apr 28, 1981
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned method for making bipolar transistor having minimum ba...
- Patent number 4,252,582
- Issue date Feb 24, 1981
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance bipolar device and method for making same
- Patent number 4,236,294
- Issue date Dec 2, 1980
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating vertical NPN and PNP structures and the resu...
- Patent number 4,214,315
- Issue date Jul 22, 1980
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral PNP or NPN with a high gain
- Patent number 4,196,440
- Issue date Apr 1, 1980
- International Business Machines Corporation
- Narasipur G. Anantha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE RANDOM LOGIC ARRAYS USING PN ISOLATION
- Publication number 20080032460
- Publication date Feb 7, 2008
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable random logic arrays using PN isolation
- Publication number 20070045733
- Publication date Mar 1, 2007
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTELLIGENT SENSOR NETWORK
- Publication number 20060280129
- Publication date Dec 14, 2006
- International Business Machines Corporation
- Eric V. Kline
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NESTED DESIGN APPROACH
- Publication number 20050278674
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED INDUCTOR AND METHOD OF MAKING
- Publication number 20050150106
- Publication date Jul 14, 2005
- David Clifford Long
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MLC frequency selective circuit structures
- Publication number 20040113721
- Publication date Jun 17, 2004
- International Business Machines Corporation
- Harsaran S. Bhatia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Embedded inductor and method of making
- Publication number 20030112114
- Publication date Jun 19, 2003
- International Business Machines Corporation
- David Clifford Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE DESIGN OF A CHIP USING A GENERIC SUBSTRATE DESIGN
- Publication number 20030047352
- Publication date Mar 13, 2003
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and circuit for electrical testing of isolation resistance o...
- Publication number 20030042910
- Publication date Mar 6, 2003
- International Business Machines, Corporation
- Harsaran S. Bhatia
- G01 - MEASURING TESTING

Harsaran S. Bhatia

Person

Patents Grantslast 30 patents

Programmable random logic arrays using PN isolation

Intelligent sensor network

Programmable random logic arrays using PN isolation

Nested design approach

Embedded inductor and method of making

Method of forming a dielectric substrate having a multiturn inductor

MLC frequency selective circuit structures

Method and circuit for electrical testing of isolation resistance o...

Substrate design of a chip using a generic substrate design

Corrosion-free multi-layer conductor

Process for corrosion free multi-layer metal conductors

Direct distribution repair and engineering change system

Schottky diode having limited area self-aligned guard ring and meth...

Electronic EC for minimizing EC pads

Dotting circuit with inhibit function

Structure for contacting a narrow width PN junction region

Method for making Schottky diode having limited area self-aligned g...

Method and resulting structure for selective multiple base width tr...

Method for contacting a narrow width PN junction region

Method for making high sheet resistivity resistors

High density memory cell

Memory cell resistor device

Method of planarizing silicon dioxide in semiconductor devices

Method for avoiding residue on a vertical walled mesa

Method for making stable nitride-defined Schottky barrier diodes

Method for making a lateral PNP or NPN with a high gain utilizing r...

Self aligned method for making bipolar transistor having minimum ba...

High performance bipolar device and method for making same

Method for fabricating vertical NPN and PNP structures and the resu...

Lateral PNP or NPN with a high gain

Patents Applicationslast 30 patents

PROGRAMMABLE RANDOM LOGIC ARRAYS USING PN ISOLATION

Programmable random logic arrays using PN isolation

INTELLIGENT SENSOR NETWORK

NESTED DESIGN APPROACH

EMBEDDED INDUCTOR AND METHOD OF MAKING

MLC frequency selective circuit structures

Embedded inductor and method of making

SUBSTRATE DESIGN OF A CHIP USING A GENERIC SUBSTRATE DESIGN

Method and circuit for electrical testing of isolation resistance o...