Harsh Rawat

Person

Faridabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Built-in self test circuit for segmented static random access memor...
- Patent number 12,170,120
- Issue date Dec 17, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Hitesh Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with fast, controlled peak current, power efficient array rese...
- Patent number 12,159,689
- Issue date Dec 3, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power and fast memory reset
- Patent number 12,068,026
- Issue date Aug 20, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory architecture with gated sub-array operation dependen...
- Patent number 12,046,324
- Issue date Jul 23, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory supporting a single clock cycle read-mo...
- Patent number 12,040,013
- Issue date Jul 16, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive bit line overdrive control for an in-memory compute operat...
- Patent number 11,984,151
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable pseudo dual port architecture for use with single port...
- Patent number 10,249,363
- Issue date Apr 2, 2019
- STMicroelectronics International N.V.
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable pseudo dual port architecture for use with single port...
- Patent number 10,032,506
- Issue date Jul 24, 2018
- STMicroelectronics International N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage selftime tracking circuitry for write assist based memo...
- Patent number 9,786,364
- Issue date Oct 10, 2017
- STMicroelectronics International N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache memory system with simultaneous read-write in single cycle
- Patent number 9,524,242
- Issue date Dec 20, 2016
- STMicroelectronics International N.V.
- Piyush Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo dual port memory using a dual port cell and a single port ce...
- Patent number 9,311,990
- Issue date Apr 12, 2016
- STMicroelectronics International N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Repair control logic for safe memories having redundant elements
- Patent number 9,208,040
- Issue date Dec 8, 2015
- STMicroelectronics International N.V.
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing of a memory with redundancy elements
- Patent number 8,458,545
- Issue date Jun 4, 2013
- STMicroelectronics International N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Balanced sense amplifier for single ended bitline memory architecture
- Patent number 8,144,537
- Issue date Mar 27, 2012
- STMicroelectronics Pvt. Ltd.
- Anand Kumar Mishra
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20240395319
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...
- Publication number 20240177769
- Publication date May 30, 2024
- STMicroelectronics International N.V.
- Promod KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...
- Publication number 20240143239
- Publication date May 2, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240069096
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071429
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071439
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...
- Publication number 20230410892
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230410862
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...
- Publication number 20230386566
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230386565
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230386564
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...
- Publication number 20230280915
- Publication date Sep 7, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20230102492
- Publication date Mar 30, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...
- Publication number 20230050783
- Publication date Feb 16, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...
- Publication number 20230051672
- Publication date Feb 16, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...
- Publication number 20230012567
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20230018420
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER AND FAST MEMORY RESET
- Publication number 20230015002
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20230008833
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230009329
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230012303
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230008275
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT...
- Publication number 20180301186
- Publication date Oct 18, 2018
- STMicroelectronics International N.V.
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT...
- Publication number 20180166128
- Publication date Jun 14, 2018
- STMicroelectronics International N.V
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS
- Publication number 20150317225
- Publication date Nov 5, 2015
- STMicroelectronics International N.V
- Harsh Rawat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY SYSTEM WITH SIMULTANEOUS READ-WRITE IN SINGLE CYCLE
- Publication number 20150212945
- Publication date Jul 30, 2015
- STMicroelectronics International N.V
- Piyush Jain
- G06 - COMPUTING CALCULATING COUNTING

Harsh Rawat

Person

Patents Grantslast 30 patents

Built-in self test circuit for segmented static random access memor...

SRAM with fast, controlled peak current, power efficient array rese...

Serial word line actuation with linked source voltage supply modula...

Low power and fast memory reset

Modular memory architecture with gated sub-array operation dependen...

Static random access memory supporting a single clock cycle read-mo...

Adaptive bit line overdrive control for an in-memory compute operat...

Configurable pseudo dual port architecture for use with single port...

Configurable pseudo dual port architecture for use with single port...

Low voltage selftime tracking circuitry for write assist based memo...

Cache memory system with simultaneous read-write in single cycle

Pseudo dual port memory using a dual port cell and a single port ce...

Repair control logic for safe memories having redundant elements

Method and apparatus for testing of a memory with redundancy elements

Balanced sense amplifier for single ended bitline memory architecture

Patents Applicationslast 30 patents

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...

STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...

MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

LOW POWER AND FAST MEMORY RESET

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...

CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT...

CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT...

REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS

CACHE MEMORY SYSTEM WITH SIMULTANEOUS READ-WRITE IN SINGLE CYCLE