Patent Application
20240071439
Embodiments herein relate to a memory architecture and, in particular, to memory support of both conventional memory access mode and digital in-memory computation processing mode.
Reference is made to
Each SRAM cell 14 includes a word line WL and a pair of complementary bit lines BLT and BLC. The 8T-type SRAM cell would additionally include a read word line RWL and a read bit line RBL. The cells 14 in a common row of the matrix are connected to each other through a common word line WL (and through the common read word line RWL in the 8T-type implementation). The cells 14 in a common column of the matrix are connected to each other through a common pair of complementary bit lines BLT and BLC (and through the common read bit line RBL in the 8T-type implementation). Each word line WL, RWL is driven by a word line driver circuit 16 which may be implemented as a CMOS driver circuit (for example, a series connected p-channel and n-channel MOSFET transistor pair forming a logic inverter circuit). The word line signals applied to the word lines, and driven by the word line driver circuits 16, are generated from feature data input to the in-memory computation circuit 10 and controlled by a row controller circuit 18. A column processing circuit 20 senses the analog signals on the pairs of complementary bit lines BLT and BLC (and/or on the read bit line RBL) for the M columns, converts the analog signals to digital signals, performs digital calculations on the digital signals and generates a decision output for the in-memory compute operation.
Although not explicitly shown in
The row controller circuit 18 receives the feature data for the in-memory compute operation and in response thereto performs the function of selecting which ones of the word lines WL<0> to WL<N−1> (or read word lines RWL<0> to RWL<N−1>) are to be simultaneously accessed (or actuated) in parallel during an analog in-memory compute operation, and further functions to control application of pulsed signals to the word lines in accordance with that in-memory compute operation.
The implementation illustrated in
There exist a number of concerns with analog in-memory compute operations including: the parallel simultaneous word line access to the memory can lead to inadvertent bit flip which disturbs the logic state of the stored weight data; the multiply and accumulate (MAC) operation is in the form of analog signal levels on a shared signal line with analog-to-digital conversion; the computation is by nature an approximation due to analog signal level variation; and the circuit arrangement is complex and testability is a challenge. The analog in-memory computation solution is therefore not acceptable for applications needing deterministic computations such as in safety or security. It would be preferred to perform a digital or predictable computation.
A circuit includes: a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column; a word line drive circuit for each row having an output connected to drive the word line of the row; and a row decoder circuit coupled to the word line drive circuits.
A control circuit is configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory access operation and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during an in-memory computation operation.
In an embodiment, an input/output circuit for each column comprises: a plurality of bit line inputs coupled to the local bit lines of the sub-arrays; a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode; and a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding one of the plurality of bit line inputs, and configured to generate a plurality of sub-array data bits for output in the second mode. A processing circuit is configured to receive feature data and perform a computational operation as a function of the feature data and the plurality of sub-array data bits.
In another embodiment, an input/output circuit for each column comprises: a plurality of bit line inputs coupled to the local bit lines of the sub-arrays; a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode; a computation circuit configured to store feature data and perform a computational operation as a function of the feature data and a plurality of sub-array data bits present at the plurality of bit line inputs to generate a plurality of computation data bits; and a plurality of sub-array data outputs coupled to the computation circuit and configured to output plurality of computation data bits in the second mode. A processing circuit is configured to receive plurality of computation data bits and perform application specific signal processing operations.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
FIGS. 6A1-6A3 illustrate various operations of the embodiment of the control circuit and row decoder shown in
FIGS. 6A4-6A6 show timing diagrams for circuit operation corresponding to FIGS. 6A1-6A3;
FIGS. 6B1-6B3 illustrate various operations of the embodiment of the control circuit and row decoder shown in
Reference is now made to
Each SRAM memory cell 114 may comprise a 6T-type memory cell as shown in
Alternatively, each SRAM memory cell 114 may comprise an 8T-type memory cell as shown in
It will be understood that the circuit 110 may instead use a different type of memory cell, for example, any form of a bit cell, storage element or synaptic element producing a deterministic readout arranged in an array. As a non-limiting example, consideration is made for the use of a non-volatile memory (NVM) cell such as, for example, magnetoresistive RAM (MRAM) cell, Flash memory cell, phase change memory (PCM) cell or resistive RAM (RRAM) cell). In the following discussion, focus is made on the implementation using an 8T-type SRAM cell 114, but this is done by way of a non-limiting example, understanding that any suitable memory element could be used (e.g., a binary (two level) storage element or an m-ary (multi-level) storage element).
Each cell 114 includes a word line WL, a pair of complementary bit lines BLT and BLC, a read word line RWL and a read bit line RBL. The SRAM memory cells in a common row of the matrix are connected to each other through a common word line WL and through a common read word line RWL. Each of the word lines (WL and/or RWL) is driven by a word line driver circuit 116 with a word line signal generated by a row decoder circuit 118 during read and write operations. The SRAM memory cells in a common column of the matrix across the whole array 112 are connected to each other through a common pair of complementary (write) bit lines BLT and BLC. The array 112 is segmented into P sub-arrays 1130 to 113P-1. Each sub-array 113 includes M columns and N/P rows of memory cells 114. The SRAM memory cells in a common column of each sub-array 113 are connected to each other through a local read bit line RBL.
The P local read bit lines RBL0<x> to RBLP-1<x> from the sub-arrays 113 for the column x in the array 112 are coupled, along with the common pair of complementary bit lines BLT<x> and BLC<x> for the column x in the array 112, to a column input/output (I/O) circuit 120(x). Here, x=0 to M−1. A data input port (D) of the column I/O circuit 120 receives input data (user or weight data) to be written to an SRAM memory cell 114 in the column through the pair of complementary bit lines BLT, BLC in response to assertion of a word line signal in a conventional memory access mode of operation. A data output port (Q) of the column I/O circuit 120 generates output data read from an SRAM memory cell 14 in the column through the read bit line RBL in response to assertion of a read word line signal in the conventional memory access mode of operation. Additionally, the column I/O circuit 120 further includes P sub-array data output ports R0 to RP-1 to generate output data read from a memory cell 114 on the local read bit line RBL of the corresponding sub-array 1130 to 113P-1, respectively, in response to the simultaneous assertion of a plurality of read word line signals (one per sub-array 113) in a digital in-memory compute mode of operation. A digital computation processing circuit 123 performs digital computations on the output data from the sub-array data output ports R as a function of received feature data and generates a decision output for the digital in-memory compute operation. The processing circuit 123 can implement computation logic for the digital signal processing in a number of ways including: full support of Boolean operations (XOR, XNOR, NAND, NOR, etc.) and vector operations depending on system and application needs; accumulation pipeline operations where vector multiplication is supported within the memory; and matrix vector multiplication pipeline operations where output from the memory as one vector for the multiply and accumulate (MAC) function. It will be noted that the processing circuit 123 is an integral part of the digital in-memory computation circuit 110.
The computation logic for the digital signal processing performed by processing circuit 123 is closely integrated with the input/output circuits and the sub-array data output ports R0 to RP-1 to support utilization of a wide (for example, P times) vector access. There are a number of figure of merit (FOM) benefits which accrue from this solution including: enabling multi-word access in a same cycle amortizes the common logic toggling power inside the SRAM when wide vector access occurs; the use of sub-arrays 113 can reduce bit line toggling power consumption (i.e., where P word lines are asserted in parallel to access P corresponding sub-arrays); support of both, with the opportunity to toggle between, the conventional memory access mode of operation and the digital in-memory compute mode of operation; and on/off current ratio on the same bitline improves which is a key concern when the circuitry is implemented using fully-depleted silicon-on-insulator (FDSOI) technology where forward body bias is aggressively used.
It will be noted that the circuit 110 presents a conventional SRAM interface through the data input ports D and the data output ports Q in accordance with the conventional memory access mode of operation. In response to an applied memory address (Addr), the circuit supports read (via data output ports Q) and write (via data input ports D) access to a single row of memory cells 114 in the array 112 by the selected assertion of a single word line WL or RWL. The circuit further presents a sub-array processing interface through the sub-array data output ports R0 to RP-1 in accordance with the digital in-memory compute mode of operation. In response to an applied memory address (Addr), the circuit supports simultaneous read (via data output ports R0 to RP-1) access to a single row of memory cells 114 in each of the sub-arrays 1130 to 113P-1 by the simultaneous assertion of corresponding read word lines RWL. A single address can be decoded to select the plural word lines (one per sub-array 113) for assertion, or plural addresses can be decoded to select the plural word lines (one per sub-array 113) for assertion. The use plural sub-arrays 113 in this mode enables parallelism supporting very wide access for computation processing without sacrificing density. Advantageously, this digital in-memory compute mode of operation utilizes the resources of the conventional SRAM design with modified control, decoding and input/output circuits (as will be discussed herein in detail) to enable parallel access in the digital in-memory compute mode of operation with additional control to toggle between the conventional memory access mode of operation and the digital in-memory compute mode of operation as needed by the system application. This architecture brings parallelism with usage of the push rule bitcell thus enabling high density/compute density when configured for the in-memory compute mode of operation. Notwithstanding the foregoing, as noted above, usage of other bitcell types may instead be made.
A control circuit 119 controls mode operations of the circuitry within the circuit 110 responsive to the logic state of a control signal IMC. When the control signal IMC is in a first logic state (for example, logic low), the circuit 110 operates in accordance with the conventional memory access mode of operation (for writing data from data input port D to the memory array or reading data from the memory array to data output port Q). Conversely, when the control signal IMC is in a second logic state (for example, logic high), the circuit 110 operates in accordance with the digital in-memory compute mode of operation (for reading weight data from the memory array to the sub-array data output ports R).
When the circuit 110 is operating in the conventional memory access mode of operation, the row decoder circuit 118 decodes a received address (Addr), selectively actuates only one word line WL (during write) or one read word line RWL (during read) for the whole array 112 with a word line signal pulse to access a corresponding single one of the rows of memory cells 114. In write, logic states of the data at the input ports D are written by the column I/O circuits 120 through the pairs of complementary bit lines BLT, BLC to the single row of memory cells coupled to the accessed word line WL. In read, the logic states of the data stored in the single row of memory cells coupled to the accessed word line WL are output from the read bit lines RBL to the column I/O circuits 120 for output at the data output ports Q.
When the circuit 110 is operating in the digital in-memory compute mode of operation, the row decoder circuit 118 decodes a received address (Addr), selectively (and simultaneously) actuates one read word line RWL in each sub-array 113 in the memory array 112 with a word line signal pulse to access a corresponding row of memory cells 114 in each sub-array 113. The logic states of the weight data stored in the row of memory cells coupled to the accessed read word line RWL in each sub-array 113 are passed from the read bit lines RBL0<x> to RBLP-1<x> to the column I/O circuit 120 for output at the corresponding sub-array data output ports R0 to RP-1.
It will be noted that each sub-array 113 output can be considered as one subtensor/tensor for processing operations. Additionally, multiple sub-arrays 113 outputs can be grouped as a larger tensor. The grouping of sub-array outputs can be made across columns, across rows, or both. Such processing is supported through the configuration and operation of the processing circuit 123.
The architecture shown in
A block diagram of an embodiment for the column I/O circuit 120 is shown in
A sensing circuit 130 of the read logic circuit is coupled to receive the data on the P local read bit lines RBL0<x> to RBLP-1<x> and generate a sensed data bit on signal line 132. As an example, the sensing circuit 130 may comprise a logic NAND gate. The sensed data bit is applied to the first input of a multiplexer circuit 151 whose select input receives the control signal IMC. The second input of the multiplexer circuit 151 is coupled to the output of the multiplexer circuit 151. The data at the output of multiplexer circuit 151 is latched by latch circuit 134 and buffered by buffer circuit 136 for output at the data output port Q<x>. When the control signal IMC is in the first logic state (for example, logic low—when the circuit 110 is operating in accordance with the conventional memory access mode of operation), the multiplexer circuit 151 selects the data on signal line 132. Conversely, when the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation), the multiplexer circuit 151 selects the data at the output of the multiplexer circuit 151 (i.e., the data held by the latch 134).
A sensing circuit 140(y) of the read logic circuit is coupled to receive the data on the local read bit line RBLy<x> and generate a sensed data bit on signal line 142(y). Here, y=0 to P−1. As an example, each sensing circuit 140 may comprise a logic NOT gate. The sensed data bit is applied to the second input of a multiplexer circuit 150 whose select input receives the control signal IMC. The first input of the multiplexer circuit 150 is coupled to the output of the multiplexer circuit 150. The data at the output of multiplexer circuit 150 is latched by latch circuit 144(y) and buffered by buffer circuit 146(y) for output at the sub-array data output port Ry<x>. When the control signal IMC is in the first logic state (for example, logic low—when the circuit 110 is operating in accordance with the conventional memory access mode of operation), the multiplexer circuit 150 selects the data at the output of the multiplexer circuit 150 (i.e., the data held by the latch 144). Conversely, when the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation), the multiplexer circuit 150 selects the data on signal line 142.
The data bit at the input port D<x> is applied to the first input of a multiplexer 80 and a logical inversion of the data bit is applied to the second input of the multiplexer 80. The selection input of the multiplexer 80 receives a selection signal 82 whose logic state is dependent on whether the bit or the logical inversion of the bit is to be written by the write logic circuit to the memory cell over the bit lines BLT, BLC.
The data bit on the local read bit line RBLy<x> is buffered by a buffer circuit 84 and applied to the first input of a multiplexer 86 and a logical inversion of the buffered data bit is applied to the second input of the multiplexer 86. The selection input of the multiplexer 86 receives a selection signal 88 whose logic state is dependent on whether the bit or the logical inversion of the bit is to be read from the memory cell over the read bit line.
In connection with performing the operation to write weight data to the memory, a determination is made as to whether, for a given row of memory cells or for a given sub-array, there are more logic 1 bits or more logic 0 bits. In the case where there are more logic 0 bits, the selection signal 82 has a logic state to control the multiplexer circuits 80 of the column I/O circuits 120 to select the logical inversion of the data bits and those logically inverted data bits are written to the memory. A record of this is kept by the system 110 so that whenever an in-memory compute operation accesses weight data stored as logically inverted, the selection signal 88 has a logic state to control the multiplexer circuits 86 of the column I/O circuits 120 to select the logical inversion of the data bits and those logically inverted data bits are processed by the sensing circuits 140.
Consider the example where logic state analysis of the weight data is made at the level of the sub-array 113. If the weight data to be stored in a given sub-array includes more logic 0 bits, the data inversion signal Dinv for that sub-array is latched in an asserted state. Responsive to sub-array decoder 90 selection of that sub-array for a data write operation, a multiplexer circuit 92 is controlled to select the asserted data inversion signal Dinv for application as signal 82 and the multiplexer 80 selects the logically inverted data bit for writing to the memory. Responsive to a data read in connection with an in-memory compute operation, the asserted data inversion signal Dinv is applied as signal 88 and the multiplexer 86 selects the logically inverted data bit for read from the memory.
It will be noted that polarity inversion control can be specific to a group of subtensor segments that make up the full tensor readout. Because the logic states of the weight data are pre-known, the logic states of the data inversion signals Dinv can be selected and latched. Data polarity control can be made specific to each sub-tensor array in order to control the state of the data stored in each row of the sub-array (acting as on subtensor/tensor) based on data sparsity.
The example shown in
Reference is now made to
The circuit 110 is further configured to receive a P-bit mask signal MSK. The bits of this mask signal function as sub-decoder circuit enable signals. If the bit z of the mask signal MSK<z> is in a first logic state (for example, logic low), the corresponding sub-decoder circuit 118z is enabled and will generate a word line signal for application to one word line of the corresponding sub-array 113z. However, if the bit z of the mask signal MSK<z> is in a second logic state (for example, logic high), the corresponding sub-decoder circuit 118z is disabled and will not generate a word line signal for application to one word line of the corresponding sub-array 113z. It will be noted that exercising control over word line signal generation using the mask signal MSK is applicable only when the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation).
FIG. 6A1 shows an example of operation of the circuitry of
FIG. 6A2 shows an example of operation of the circuitry of
FIG. 6A3 shows an example of operation of the circuitry of
With reference once again to
For the example shown in FIG. 6A1, where IMC=0, consider that AddressK=Addr<0,1,1,1,0>. This is decoded to identify word line WL<14> when writing to the memory (or RWL<14> when reading from the memory), and sub-decoder 1181 will generate the word line signal on only that word line. No other sub-decoders 118 will generate a word line signal. The timing for this operation is shown in FIG. 6A4 (where word line signal WL<-> (and RWL<->) is logic low for all word lines other than the selected word line WL<14> (or RWL<14>). Note also that the data output Q may change state in response to the memory read operation, and there is no change in state for the sub-array data outputs R0-R3 (because the digital in-memory compute mode of operation is not enabled by the signal IMC and the multiplexers 150 are holding the data values of the latches 144).
For the example shown in FIG. 6A2, where IMC=1, consider that AddressJ=Addr<0,1,1,1,0> and the mask signal is MSK<0,0,0,0>. This address is decoded to identify word lines RWL<6>, RWL<14>, RWL<22> and RWL<30> and sub-decoder 1180 will generate the word line signal on word line RWL<6> (because corresponding MSK bit is 0), sub-decoder 1181 will generate the word line signal on word line RWL<14> (because corresponding MSK bit is 0), sub-decoder 1182 will generate the word line signal on word line RWL<22> (because corresponding MSK bit is 0), and sub-decoder 1183 will generate the word line signal on word line RWL<30> (because corresponding MSK bit is 0). No other word lines will be selected by the sub-decoders 118 for generating a word line signal. The timing for this operation is shown in FIG. 6A5 (where word line signal RWL<-> is logic low for all word lines other than the selected and non-masked word lines RWL<6>, RWL<14>, RWL<22> and RWL<30>). Note also that the sub-array data outputs R0-R3 may change state in response to the memory read operation, and there is no change in state for the data output Q (because the conventional mode of operation is not enabled by the signal IMC and the multiplexer 151 is holding the data value of the latch 134).
For the example shown in FIG. 6A3, where IMC=1, consider that AddressJ=Addr<0,1,1,1,0> and the mask signal MSK<0,0,0,1>. This address is decoded to identify word lines RWL<6>, RWL<14>, RWL<22> and RWL<30> and sub-decoder 1180 will NOT generate a word line signal on word line RWL<6> (because corresponding MSK bit is 1 and the sub-decoder is disabled), sub-decoder 1181 will generate the word line signal on word line RWL<14> (because corresponding MSK bit is 0), sub-decoder 1182 will generate the word line signal on word line RWL<22> (because corresponding MSK bit is 0), and sub-decoder 1183 will generate the word line signal on word line RWL<30> (because corresponding MSK bit is 0). No other word lines will be selected by the sub-decoders 118 for generating a word line signal. The timing for this operation is shown in FIG. 6A6 (where word line signal RWL<-> is logic low for all word lines other than the selected and non-masked word lines RWL<14>, RWL<22> and RWL<30>, and where masked word line RWL<6> is also logic low). Note also that the sub-array data outputs R1-R3 may change state in response to the memory read operation, but that sub-array data output R0 will not change state because of the masking by mask signal MSK which disables sub-decoder 1180, and there is no change in state for the data output Q (because the conventional mode of operation is not enabled by the signal IMC and the multiplexer 151 is holding the data value of latch 134).
Reference is now made to
The selection input of the multiplexer circuit 117 receives the control signal IMC. If the control signal IMC is in the first logic state (for example, logic low—when the circuit 110 is operating in accordance with the conventional memory access mode of operation), the multiplexer circuit 117 selects decoder control signals 121-M for output as the decoder control signals 121 to each of the sub-decoder circuits 1180 to 118P-1. The first address predecoding circuit of the control circuit 119 decodes the address M-Addr to generate the decoder control signals 121-M, 121 in a way which will result in only one of the sub-decoder circuits 1180 to 118P-1 generating a word line signal for application to only one word line for the array 112. However, if the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation), the multiplexer circuit 117 selects decoder control signals 121-IMC for output as the decoder control signals 121 to each of the sub-decoder circuits 1180 to 118P-1. The second address predecoding circuit of the control circuit 119 decodes each of the addresses IMC-Addr0 to IMC-AddrP−1 to generate the decoder control signals 121-IMC, 121 in a way which will result in each of the sub-decoder circuits 1180 to 118P-1 generating a word line signal for application to one word line per sub-array 113. In particular, each address IMC-Addr when decoded will specify a certain one of the word lines of the corresponding sub-array 113 to which the word line signal is to be applied.
The circuit 110 is further configured to receive a P-bit mask signal MSK. The bits of this mask signal function as sub-decoder circuit enable signals. If the bit z of the mask signal MSK<z> is in a first logic state (for example, logic low), the corresponding sub-decoder circuit 118z is enabled and will generate a word line signal for application to one word line of the corresponding sub-array 113z. However, if the bit z of the mask signal MSK<z> is in a second logic state (for example, logic high), the corresponding sub-decoder circuit 118z is disabled and will not generate a word line signal for application to one word line of the corresponding sub-array 113z. It will be noted that exercising control over word line signal generation using the mask signal MSK is applicable only when the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation).
FIG. 6B1 shows an example of operation of the circuitry of
In the context of the previous table for full address decoding function performed by the control circuit 119 and row decoder 118, consider the scenario where IMC=0 and M-Addr<0,1,1,1,0>. This is decoded to identify word line WL<14> when writing to the memory (or RWL<14> when reading from the memory), and sub-decoder 1181 will generate the word line signal on only that word line. No other sub-decoders 118 will generate a word line signal. The timing for this operation is similar to that shown in FIG. 6A4 (where word line signal WL<-> (and RWL<->) is logic low for all word lines other than the selected word line WL<14> (or RWL<14>)). Note also that the data output Q may change state in response to the memory read operation, and there is no change in state for the sub-array data outputs R0-R4 (because the digital in-memory compute mode of operation is not enabled by the signal IMC and the multiplexers 150 are holding the data values of the latches 144).
FIG. 6B2 shows an example of operation of the circuitry of
In the context of the previous table for full address decoding function performed by the control circuit 119 and row decoder 118, consider the scenario where IMC=1, the mask signal MSK<0,0,0,0>, IMC-Addr0<0,0,1,1,0>, IMC-Addr1<0,1,1,1,0>, IMC-Addr2<1,0,1,1,0> and IMC-Addr3<1,1,1,1,0>. These addresses are decoded to identify word lines RWL<6>, RWL<14>, RWL<22> and RWL<30> and sub-decoder 1180 will generate the word line signal on RWL<6> (because corresponding MSK bit is 0), sub-decoder 1181 will generate the word line signal on word line RWL<14> (because corresponding MSK bit is 0), sub-decoder 1182 will generate the word line signal on word line RWL<22> (because corresponding MSK bit is 0), and sub-decoder 1183 will generate the word line signal on word line RWL<30> (because corresponding MSK bit is 0). No other word lines will be selected by the sub-decoders 118 for generating a word line signal. The timing for this operation is similar to that shown in FIG. 6A5 (where word line signal RWL<-> is logic low for all word lines other than the selected and non-masked word lines RWL<6>, RWL<14>, RWL<22> and RWL<30> and Addr=[IMC-Addr0, IMC-Addr1, IMC-Addr2> and IMC-Addr3]). Note also that the sub-array data outputs R0-R3 may change state in response to the memory read operation, and there is no change in state for the data output Q (because the conventional mode of operation is not enabled by the signal IMC and the multiplexer 151 is holding the data value of the latch 134).
FIG. 6B3 shows an example of operation of the circuitry of
In the context of the previous table for full address decoding function performed by the control circuit 119 and row decoder 118, consider the scenario where IMC=1, and the mask signal MSK<0,0,0,1>, IMC-Addr0<0,0,1,1,0>, IMC-Addr1<0,1,1,1,0>, IMC-Addr2<1,0,1,1,0> and IMC-Addr3<1,1,1,1,0>. These addresses are decoded to identify word lines RWL<6>, RWL<14>, RWL<22> and RWL<30> and sub-decoder 1180 will NOT generate the word line signal on RWL<6> (because corresponding MSK bit is 1), sub-decoder 1181 will generate the word line signal on word line RWL<14> (because corresponding MSK bit is 0), sub-decoder 1182 will generate the word line signal on word line RWL<22> (because corresponding MSK bit is 0), and sub-decoder 1183 will generate the word line signal on word line RWL<30> (because corresponding MSK bit is 0). No other word lines will be selected by the sub-decoders 118 for generating a word line signal. The timing for this operation is similar to that shown in FIG. 6A6 (where word line signal RWL<-> is logic low for all word lines other than the selected and non-masked word lines RWL<14>, RWL<22> and RWL<30>, and where masked word line RWL<6> is also logic low, and Addr=[IMC-Addr0, IMC-Addr1, IMC-Addr2> and IMC-Addr3]). Note also that the sub-array data outputs R1-R3 may change state in response to the memory read operation, but that sub-array data output R0 will not change state because of the masking by mask signal MSK which disables sub-decoder 1180, and there is no change in state for the data output Q (because the conventional mode of operation is not enabled by the signal IMC and the multiplexer 151 is holding the data value of the latch 134).
Reference is now made to
The P local read bit lines RBL0<x> to RBLP-1<x> from the sub-arrays 113 for the column x in the array 112 are coupled, along with the common pair of complementary bit lines BLT<x> and BLC<x> for the column x in the array 112, to the column I/O circuit 220(x). Here, x=0 to M−1. A data input port (D) of the column I/O circuit 220 receives input data (user or weight data) to be written to an SRAM memory cell 114 in the column through the pair of complementary bit lines BLT, BLC in response to assertion of a word line signal in a conventional memory access mode of operation. A data output port (Q) of the column I/O circuit 220 generates output data read from an SRAM memory cell 14 in the column through the read bit line RBL in response to assertion of a read word line signal in the conventional memory access mode of operation. Additionally, the column I/O circuit 220 further includes P sub-array data output ports R0 to RP-1 to generate computational output data.
A block diagram of an embodiment for the column I/O circuit 220 is shown in
A sensing circuit 140(y) of the read logic circuit is coupled to receive the data on the local read bit line RBLy<x> and generate a sensed data bit on signal line 142(y). Here, y=0 to P−1. As an example, each sensing circuit 140 may comprise a logic NOT gate. The sensed data bit is applied to a feature data buffer and computation (FD+Comp) circuit 222(y). It will be noted that there can be a plurality of these feature data slices which have a certain desired correspondence with the sub-arrays 113 (this correspondence being, for example, a one-to-one correspondence where certain feature data is unique to a certain sub-array or a one-to-many correspondence where certain feature data is applicable to multiple sub-arrays). The FD+Comp circuit 222(y) stores a feature data bit and operates to perform a digital computation (for example, a Boolean operation such as an XOR operation) on the sensed data bit received on signal line 142(y) with the stored feature data bit. A computational output data bit generated as a result of performing the digital computation is applied to the second input of a multiplexer circuit 150 whose select input receives the control signal IMC. The first input of the multiplexer circuit 150 is coupled to the output of the multiplexer circuit 150. The computational output data bit at the output of multiplexer circuit 150 is latched by latch circuit 144(y) and buffered by buffer circuit 146(y) for output at the sub-array data output port Ry<x>. When the control signal IMC is in the first logic state (for example, logic low—when the circuit 110 is operating in accordance with the conventional memory access mode of operation), the multiplexer circuit 150 selects the data at the output of the multiplexer circuit 150 (i.e., the data held by the latch 144). Conversely, when the control signal IMC is in the second logic state (for example, logic high—when the circuit 110 is operating in accordance with the digital in-memory compute mode of operation), the multiplexer circuit 150 selects the data on signal line 142.
It will be noted that the FD+Comp circuits 222(y) within a given column I/O circuit 220 may be programmed to store the same bit of feature data. Alternatively, each FD+Comp circuit 222(y) within a given column I/O circuit 220 may be individually programmable and thus capable of storing different bits of feature data. In either case, the bits of the feature data are written into latch circuitry for storage in the FD+Comp circuits 222(y). The writing of feature data bits into each FD+Comp circuit 222(y) is enabled by the assertion of a feature word line signal on a feature word line FWL<0:K−1>. The word line signal on the feature word line FWL may be generated, for example, by the row decoder circuit 118 in connection with generating the word line signal(s) on the word lines WL and/or RWL. Alternatively, the word line signal on the feature word line FWL may be generated by the control circuit 119 in connection with performing the address decoding operation.
The data on the feature word line FWL may have a one-to-many or one-to-one relationship with the sub-arrays 113. Thus, certain feature data on the feature word line FWL<0:K−1> may be applied to the outputs from plural sub-arrays (one-to-many), or certain feature data on the feature word line may be specific to the output from a corresponding certain sub-array (one-to-one).
Reference is now made to
The second bit cell 232 includes two cross-coupled CMOS inverters 262 and 264, each inverter including a series connected p-channel and n-channel MOSFET transistor pair. The inputs and outputs of the inverters 262 and 264 are coupled to form a latch circuit having a second true data storage node QT2 and a second complement data storage node QC2 which store complementary logic states of the stored feature data bit. The second bit cell 232 further includes two transfer (passgate) transistors 266 and 268 whose gate terminals are driven by a word line WL. The source-drain path of transistor 266 is connected between the second true data storage node QT2 and a node associated with the true write bit line WBLT. The source-drain path of transistor 268 is connected between the second complement data storage node QC2 and a node associated with the write complement bit line WBLC. The source terminals of the p-channel transistors 270 and 272 in each inverter 262 and 264 are coupled to receive a high supply voltage (for example, Vdd) at a high supply node, while the source terminals of the n-channel transistors 274 and 276 in each inverter 262 and 264 are coupled to receive a low supply voltage (for example, ground (Gnd) reference) at a low supply node. A signal path between the XOR output bit line XORBL (corresponding to signal line 142(y) and the low supply voltage reference is formed by series coupled transistors 278 and 280. The gate terminal of the (read) transistor 278 is coupled to the second true storage node QT2 and the gate terminal of the (transfer) transistor 280 is coupled to receive the logical inversion (by way of NOT logic gate 290) of the signal on the read bit line RBLy<x>.
The logical XOR operation is performed within each FD+Comp circuit 222(y) by the arrangement of transistors 258 and 278 (gate controlled by complementary logic states of the feature data bit stored by the latch circuits in the first and second bit cells 230, 232) and respectively series connected transistors 260 and 280 (gate controlled by complementary logic states of the weight bit read from the array 112 through the read bit line RBLy<x>).
The true write bit line WBLT and the write complement bit line WBLC are coupled to data write circuitry (not explicitly shown) which can write feature data bits to the latch circuits of the first bit cell 230 and the second bit cell 232 when a feature word line signal is asserted on the feature word line FWL.
A bit line precharge circuit 292 is provided to precharge a Vdd voltage level on the true write bit line WBLT and the write complement bit line WBLC in response to a precharge control signal PCH. Likewise, a bit line precharge circuit 293 is provided to precharge a Vdd voltage level on the XOR output bit line XORBL in response to a precharge control signal PCH.
The precharge control signal PCH is further applied to enable a data latching function performed by a latch circuit 296 on the computational output data bit generated on the XOR output bit line XORBL (signal line 142(y)). In an implementation, the latch circuit 296 may comprise, for example, a D-type flip-flop latch enabled by assertion of the precharge control signal PCH.
With reference once again to
With reference once again to
Although the circuit design of the FD+Comp circuit 222(y) shown in
The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.
This application claims priority to United States Provisional Application for Patent No. 63/402,208, filed Aug. 30, 2022, the disclosure of which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63402208 | Aug 2022 | US |
