Hartmud Terletzki

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shallow trench isolation area having buried capacitor
- Patent number 10,068,897
- Issue date Sep 4, 2018
- Infineon Technologies AG
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation area having buried capacitor
- Patent number 9,536,872
- Issue date Jan 3, 2017
- Infineon Technologies AG
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Level-shifting circuitry having “high” output impedance during disa...
- Patent number 7,173,473
- Issue date Feb 6, 2007
- Infineon Technologies AG
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple chip semiconductor arrangement having electrical component...
- Patent number 7,060,529
- Issue date Jun 13, 2006
- Infineon Technologies AG
- Manfred Reithinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using isolated p-well transistor arrangements to avoid leakage caus...
- Patent number 6,930,930
- Issue date Aug 16, 2005
- Infineon Technologies AG
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Level-shifting circuitry having “high” output impedance during disa...
- Patent number 6,853,233
- Issue date Feb 8, 2005
- Infineon Technologies AG
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple chip semiconductor arrangement having electrical component...
- Patent number 6,815,803
- Issue date Nov 9, 2004
- Infineon Technologies AG
- Manfred Reithinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method
- Patent number 6,730,989
- Issue date May 4, 2004
- Infineon Technologies AG
- Manfred Reithinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Twisted bit-line compensation
- Patent number 6,608,783
- Issue date Aug 19, 2003
- Infineon Technologies North America Corp.
- Gerd Frankowsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Level-shifting circuitry having “low” output during...
- Patent number 6,501,298
- Issue date Dec 31, 2002
- Infineon Technologies AG
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level-shifting circuitry having “high” output durin...
- Patent number 6,459,300
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse width detection
- Patent number 6,400,650
- Issue date Jun 4, 2002
- Infineon Technologies AG
- Gerd Frankowsky
- G01 - MEASURING TESTING
Information Patent Grant
Pulse width detection
- Patent number 6,324,125
- Issue date Nov 27, 2001
- Infineon Technologies AG
- Gerd Frankowsky
- G01 - MEASURING TESTING
Information Patent Grant
Constant current CMOS output driver circuit with dual gate transist...
- Patent number 5,939,937
- Issue date Aug 17, 1999
- Siemens Aktiengesellschaft
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Shallow Trench Isolation Area Having Buried Capacitor
- Publication number 20170084607
- Publication date Mar 23, 2017
- INFINEON TECHNOLOGIES AG
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow Trench Isolation Area Having Buried Capacitor
- Publication number 20150041949
- Publication date Feb 12, 2015
- INFINEON TECHNOLOGIES AG
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Level-shifting circuitry having "high" output impedance during disa...
- Publication number 20050122156
- Publication date Jun 9, 2005
- Hartmud Terletzki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multiple chip semiconductor arrangement having electrical component...
- Publication number 20050001298
- Publication date Jan 6, 2005
- Manfred Reithinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using isolated p-well transistor arrangements to avoid leakage caus...
- Publication number 20040084703
- Publication date May 6, 2004
- Hartmud Terletzki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWISTED BIT-LINE COMPENSATION
- Publication number 20030133320
- Publication date Jul 17, 2003
- Gerd Frankowsky
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array employing integral isolation transistors
- Publication number 20030062556
- Publication date Apr 3, 2003
- Hartmud Terletzki
- G11 - INFORMATION STORAGE

Hartmud Terletzki

Person

Patents Grantslast 30 patents

Shallow trench isolation area having buried capacitor

Shallow trench isolation area having buried capacitor

Level-shifting circuitry having “high” output impedance during disa...

Multiple chip semiconductor arrangement having electrical component...

Using isolated p-well transistor arrangements to avoid leakage caus...

Level-shifting circuitry having “high” output impedance during disa...

Multiple chip semiconductor arrangement having electrical component...

Semiconductor package and method

Twisted bit-line compensation

Level-shifting circuitry having &#x0201C;low&#x0201D; output during...

Level-shifting circuitry having &#x0201C;high&#x0201D; output durin...

Pulse width detection

Pulse width detection

Constant current CMOS output driver circuit with dual gate transist...

Patents Applicationslast 30 patents

Shallow Trench Isolation Area Having Buried Capacitor

Shallow Trench Isolation Area Having Buried Capacitor

Level-shifting circuitry having "high" output impedance during disa...

Multiple chip semiconductor arrangement having electrical component...

Using isolated p-well transistor arrangements to avoid leakage caus...

TWISTED BIT-LINE COMPENSATION

Memory array employing integral isolation transistors

Level-shifting circuitry having “low” output during...

Level-shifting circuitry having “high” output durin...