Claims
- 1. A semiconductor circuit comprising:operational circuitry configured to produce a signal, having at least one pulse, to be tested; test circuitry configured to sense the signal at an effective sampling frequency, and to produce an indication of a characteristic of the at least one pulse, the indication being detectable at a frequency lower than the effective sampling frequency, the test circuitry being operated independently of a clock signal having a clock frequency that is greater than the effective sampling frequency.
- 2. The circuit recited in claim 1 wherein the test circuitry is configured to produce an indication of a time duration of a pulse in the signal.
- 3. A system for testing a semiconductor circuit, the system comprising:a semiconductor circuit including: a circuit for producing a signal pulse having a pulse time duration; and a test circuit adapted to measure the signal pulse and to provide a digitized indication of a selected one of a plurality of windows of time durations, having corresponding timespans, that includes the pulse time duration; and a tester adapted to couple to the semiconductor circuit to detect the digitized indication, the tester having an operating frequency that is lower than an inverse of a shortest one of the timespans.
- 4. The system recited in claim 3 wherein the semiconductor circuit further includes a plurality of output pins, the digitized indication being provided to at least one of the output pins, the tester being adapted to couple to the output pins.
- 5. A semiconductor circuit comprising:operational circuitry configured to produce a signal, having a pulse, to be tested; test circuitry configured to sense the signal and to provide indications of whether the pulse has a time duration at least as long as corresponding, different, time durations, the time durations defining a plurality of time windows indicative of different ranges of time durations, with differences between maximum time durations and minimum time durations of respective time windows being timespans of the respective time windows, the indications having a first frequency, f1, that is lower than a second frequency, f2, defined by an inverse of a shortest one of the timespans, the test circuitry operating independently of a clock signal having a clock frequency, fCLK, that is greater than the second frequency f2.
Parent Case Info
This is a divisional, of application Ser. No. 09/281,020 filed Mar. 30, 1999, U.S. Pat. No. 6,324,825.
US Referenced Citations (5)