Helmut Puchner

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory cell array latchup prevention
- Patent number 9,842,629
- Issue date Dec 12, 2017
- Cypress Semiconductor Corporation
- Ravindra M Kapre
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High reliability non-volatile static random access memory devices,...
- Patent number 9,570,152
- Issue date Feb 14, 2017
- Cypress Semiconductor Corporation
- Suhail Zain
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS type stacks for nonvolatile charge trap memory devices and me...
- Patent number 9,553,175
- Issue date Jan 24, 2017
- Cypress Semiconductor Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory controller devices, systems and methods for translating memo...
- Patent number 9,304,953
- Issue date Apr 5, 2016
- Cypress Semiconductor Corporation
- Suhail Zain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SONOS type stacks for nonvolatile changetrap memory devices and met...
- Patent number 9,105,740
- Issue date Aug 11, 2015
- Cypress Semiconductor Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High reliability non-volatile static random access memory devices,...
- Patent number 8,861,271
- Issue date Oct 14, 2014
- Cypress Semiconductor Corporation
- Suhail Zain
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit with electrostatic discharge protection
- Patent number 8,841,727
- Issue date Sep 23, 2014
- Cypress Semiconductor Corporation
- Andrew Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit with electrostatic discharge protection
- Patent number 8,283,727
- Issue date Oct 9, 2012
- Cypress Semiconductor Corporation
- Andrew Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage protection device
- Patent number 8,278,684
- Issue date Oct 2, 2012
- Cypress Semiconductor Corporation
- Andrew J. Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SONOS type stacks for nonvolatile change trap memory devices and me...
- Patent number 8,163,660
- Issue date Apr 24, 2012
- Cypress Semiconductor Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit with electrostatic discharge protection
- Patent number 8,143,673
- Issue date Mar 27, 2012
- Cypress Semiconductor Corporation
- Andrew Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor triggered silicon controlled rectifier
- Patent number 8,129,788
- Issue date Mar 6, 2012
- Cypress Semiconductor Corporation
- Andrew Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and circuit for reducing degradation in a regulated circuit
- Patent number 8,063,655
- Issue date Nov 22, 2011
- Cypress Semiconductor Corporation
- Helmut Puchner
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage diode
- Patent number 7,936,023
- Issue date May 3, 2011
- Cypress Semiconductor Corporation
- Jaejune Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory and method of operating the same
- Patent number 7,859,899
- Issue date Dec 28, 2010
- Cypress Semiconductor Corporation
- Kaveh Shakeri
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits providing ESD protection to high voltage laterally diffuse...
- Patent number 7,838,937
- Issue date Nov 23, 2010
- Cypress Semiconductor Corporation
- Andrew J. Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Drain extended MOS transistor with increased breakdown voltage
- Patent number 7,768,068
- Issue date Aug 3, 2010
- Cypress Semiconductor Corporation
- Kevin Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection device
- Patent number 7,667,241
- Issue date Feb 23, 2010
- Cypress Semiconductor Corporation
- Andrew Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon controlled rectifier electrostatic discharge clamp for a hi...
- Patent number 7,659,558
- Issue date Feb 9, 2010
- Cypress Semiconductor Corporation
- Andrew J. Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS embedded high voltage transistor
- Patent number 7,592,661
- Issue date Sep 22, 2009
- Cypress Semiconductor Corporation
- Sungkwon Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming super-steep diffusion region profiles in MOS de...
- Patent number 7,105,413
- Issue date Sep 12, 2006
- Cypress Semiconductor Corp.
- Jeong-Yeop Nahm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon germanium CMOS channel
- Patent number 6,977,400
- Issue date Dec 20, 2005
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit isolation system
- Patent number 6,831,348
- Issue date Dec 14, 2004
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for etching a controllable thickness of oxide on an integra...
- Patent number 6,759,337
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation structure for laser thermal processing
- Patent number 6,734,081
- Issue date May 11, 2004
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of metal contacts for deep-submicron technologies
- Patent number 6,727,165
- Issue date Apr 27, 2004
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit isolation system
- Patent number 6,613,651
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow junction formation
- Patent number 6,605,846
- Issue date Aug 12, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon germanium CMOS channel
- Patent number 6,544,854
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming high dielectric constant gate dielectric for in...
- Patent number 6,511,925
- Issue date Jan 28, 2003
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Met...
- Publication number 20160104789
- Publication date Apr 14, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL ARRAY LATCHUP PREVENTION
- Publication number 20140211547
- Publication date Jul 31, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ravindra M Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND MET...
- Publication number 20140103418
- Publication date Apr 17, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Helmut PUCHNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY...
- Publication number 20140006730
- Publication date Jan 2, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Suhail Zain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Met...
- Publication number 20100041222
- Publication date Feb 18, 2010
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and circuit for reducing degradation in a regulated circuit
- Publication number 20070018678
- Publication date Jan 25, 2007
- Cypress Semiconductor Corporation
- Helmut Puchner
- G11 - INFORMATION STORAGE
Information Patent Application
Methods for forming super-steep diffusion region profiles in MOS de...
- Publication number 20050215024
- Publication date Sep 29, 2005
- Jeong-Yeop Nahm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit isolation system
- Publication number 20030162366
- Publication date Aug 28, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon germanium CMOS channel
- Publication number 20030146494
- Publication date Aug 7, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow junction formation
- Publication number 20030045062
- Publication date Mar 6, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System to improve SER immunity and punchthrough
- Publication number 20020173087
- Publication date Nov 21, 2002
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS

Helmut Puchner

Person

Patents Grantslast 30 patents

Memory cell array latchup prevention

High reliability non-volatile static random access memory devices,...

SONOS type stacks for nonvolatile charge trap memory devices and me...

Memory controller devices, systems and methods for translating memo...

SONOS type stacks for nonvolatile changetrap memory devices and met...

High reliability non-volatile static random access memory devices,...

Circuit with electrostatic discharge protection

Circuit with electrostatic discharge protection

Voltage protection device

SONOS type stacks for nonvolatile change trap memory devices and me...

Circuit with electrostatic discharge protection

Capacitor triggered silicon controlled rectifier

Method and circuit for reducing degradation in a regulated circuit

High voltage diode

Non-volatile memory and method of operating the same

Circuits providing ESD protection to high voltage laterally diffuse...

Drain extended MOS transistor with increased breakdown voltage

Electrostatic discharge protection device

Silicon controlled rectifier electrostatic discharge clamp for a hi...

CMOS embedded high voltage transistor

Methods for forming super-steep diffusion region profiles in MOS de...

Silicon germanium CMOS channel

Integrated circuit isolation system

Process for etching a controllable thickness of oxide on an integra...

Shallow trench isolation structure for laser thermal processing

Fabrication of metal contacts for deep-submicron technologies

Integrated circuit isolation system

Shallow junction formation

Silicon germanium CMOS channel

Process for forming high dielectric constant gate dielectric for in...

Patents Applicationslast 30 patents

SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Met...

MEMORY CELL ARRAY LATCHUP PREVENTION

SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND MET...

MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY...

SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Met...

Method and circuit for reducing degradation in a regulated circuit

Methods for forming super-steep diffusion region profiles in MOS de...

Integrated circuit isolation system

Silicon germanium CMOS channel

Shallow junction formation

System to improve SER immunity and punchthrough