Hidehiro Fujiwara

Person

Hsin-Chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Memory device having a negative voltage circuit
- Patent number 12,367,929
- Issue date Jul 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,369,292
- Issue date Jul 22, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Hsin Nien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage regulator with power rail tracking
- Patent number 12,346,143
- Issue date Jul 1, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Haruki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitcell supporting bit-write-mask function
- Patent number 12,334,145
- Issue date Jun 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit die with memory macro including through-silicon...
- Patent number 12,308,303
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical interconnect structures in three-dimensional integrated ci...
- Patent number 12,261,152
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tzu-Hsien Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices with improved bit line loading
- Patent number 12,260,903
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Separated read BL scheme in 3T dram for read speed improvement
- Patent number 12,260,897
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with additional write bit lines
- Patent number 12,260,904
- Issue date Mar 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell word line structure with reduced RC effects
- Patent number 12,245,412
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hidehiro Fujiwara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device including a word line with portions with different si...
- Patent number 12,230,318
- Issue date Feb 18, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
In-memory computation circuit and method
- Patent number 12,164,882
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Der Chih
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for memory operation using local word lines
- Patent number 12,159,688
- Issue date Dec 3, 2024
- Taiwan Semiconductor Manufacturing Company Limited
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Compute in memory
- Patent number 12,147,784
- Issue date Nov 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Header layout design including backside power rail
- Patent number 12,136,466
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Haruki Mori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Four CPP wide memory cell with buried power grid, and method of fab...
- Patent number 12,137,548
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of manufacturing the same
- Patent number 12,125,523
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to balance ground bounce
- Patent number 12,100,436
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including dual control circuits
- Patent number 12,080,341
- Issue date Sep 3, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing same
- Patent number 12,074,156
- Issue date Aug 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array circuit and method of manufacturing same
- Patent number 12,029,023
- Issue date Jul 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
4CPP SRAM cell and array
- Patent number 11,997,843
- Issue date May 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage regulator with power rail tracking
- Patent number 11,989,046
- Issue date May 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Haruki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vertical interconnect structures in three-dimensional integrated ci...
- Patent number 11,978,723
- Issue date May 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tzu-Hsien Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shared power footer circuit
- Patent number 11,961,554
- Issue date Apr 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory with write assist circuit
- Patent number 11,948,627
- Issue date Apr 2, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for computing-in-memory (CIM)
- Patent number 11,935,586
- Issue date Mar 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having a negative voltage circuit
- Patent number 11,929,116
- Issue date Mar 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and operating method for computing-in-memory
- Patent number 11,908,545
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit having SRAM memory cells and method for forming a SR...
- Patent number 11,910,587
- Issue date Feb 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hidehiro Fujiwara

Patents Applicationslast 30 patents

Information Patent Application
REDUCED POWER CONSUMPTION COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERA...
- Publication number 20250239998
- Publication date Jul 24, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICE
- Publication number 20250239281
- Publication date Jul 24, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki MORI
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR CONFIGURABLE ADDER CIRCUIT
- Publication number 20250231740
- Publication date Jul 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT COMPUTATION DEVICE AND METHOD
- Publication number 20250224923
- Publication date Jul 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xiaochen PENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE-IN-MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
- Publication number 20250217106
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki Mori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL-HYBRID ACCUMULATOR FLOOR PLAN FOR COMPUTE-IN-MEMORY
- Publication number 20250217299
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Je-Min Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
- Publication number 20250220868
- Publication date Jul 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT
- Publication number 20250201296
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
- Publication number 20250201322
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH IMPROVED BIT LINE LOADING
- Publication number 20250201303
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin NIEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH ADDITIONAL WRITE BIT LINES
- Publication number 20250191652
- Publication date Jun 12, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
- Publication number 20250159857
- Publication date May 15, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE INCLUDING A WORD LINE WITH PORTIONS WITH DIFFERENT SI...
- Publication number 20250157531
- Publication date May 15, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Hsin NIEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES CONFIGURED WITH PULSE ADJUSTMENT AND METHODS FOR OPE...
- Publication number 20250124966
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH SWITCHABLE POWER DELIVERY PATHS
- Publication number 20250118632
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT AND METHOD
- Publication number 20250094126
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Der CHIH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Memory Operation Using Local Word Lines
- Publication number 20250078889
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Application
Sparsity-Aware Zero Skipping for Compute-In-Memory Circuits
- Publication number 20250068390
- Publication date Feb 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Je-Min Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME
- Publication number 20250063709
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro FUJIWARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE
- Publication number 20250054537
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
- Publication number 20250046367
- Publication date Feb 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kao-Cheng Lin
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...
- Publication number 20250014614
- Publication date Jan 9, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Application
LATCH CIRCUITS AND METHODS FOR OPERATING THE SAME
- Publication number 20240429902
- Publication date Dec 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL
- Publication number 20240404566
- Publication date Dec 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki MORI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLY SHARED BIT LINE ON 4-CPP STATIC RANDOM ACCESS MEMORY (SRAM) CEL...
- Publication number 20240404588
- Publication date Dec 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNED EXTENSION CARRY-LOOK-AHEAD FOR ACCUMULATOR WITH BIT WIDTH DI...
- Publication number 20240385801
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Haruki MORI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE IN MEMORY
- Publication number 20240385803
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20240386945
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin NIEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH REDUCED BIT LINE CAPACITANCE AND METHODS OF MAN...
- Publication number 20240371412
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING DUAL CONTROL CIRCUITS
- Publication number 20240363158
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- HIDEHIRO FUJIWARA
- G11 - INFORMATION STORAGE

Hidehiro Fujiwara

Person

Patents Grantslast 30 patents

Memory device having a negative voltage circuit

Memory device

Voltage regulator with power rail tracking

Bitcell supporting bit-write-mask function

Integrated circuit die with memory macro including through-silicon...

Vertical interconnect structures in three-dimensional integrated ci...

Memory devices with improved bit line loading

Separated read BL scheme in 3T dram for read speed improvement

Memory device with additional write bit lines

SRAM cell word line structure with reduced RC effects

Memory device including a word line with portions with different si...

In-memory computation circuit and method

Systems and methods for memory operation using local word lines

Compute in memory

Header layout design including backside power rail

Four CPP wide memory cell with buried power grid, and method of fab...

Memory device and method of manufacturing the same

Method and system to balance ground bounce

Memory device including dual control circuits

Memory array circuit and method of manufacturing same

Memory array circuit and method of manufacturing same

4CPP SRAM cell and array

Voltage regulator with power rail tracking

Vertical interconnect structures in three-dimensional integrated ci...

Shared power footer circuit

Static random access memory with write assist circuit

Memory device and method for computing-in-memory (CIM)

Memory device having a negative voltage circuit

Memory device and operating method for computing-in-memory

Memory circuit having SRAM memory cells and method for forming a SR...

Patents Applicationslast 30 patents

REDUCED POWER CONSUMPTION COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERA...

MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICE

SYSTEMS AND METHODS FOR CONFIGURABLE ADDER CIRCUIT

FLOATING-POINT COMPUTATION DEVICE AND METHOD

COMPUTE-IN-MEMORY DEVICES AND METHODS FOR OPERATING THE SAME

SEQUENTIAL-HYBRID ACCUMULATOR FLOOR PLAN FOR COMPUTE-IN-MEMORY

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

MEMORY DEVICES WITH IMPROVED BIT LINE LOADING

MEMORY DEVICE WITH ADDITIONAL WRITE BIT LINES

SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS

MEMORY DEVICE INCLUDING A WORD LINE WITH PORTIONS WITH DIFFERENT SI...

MEMORY DEVICES CONFIGURED WITH PULSE ADJUSTMENT AND METHODS FOR OPE...

MEMORY DEVICES WITH SWITCHABLE POWER DELIVERY PATHS

IN-MEMORY COMPUTATION CIRCUIT AND METHOD

Systems and Methods for Memory Operation Using Local Word Lines

Sparsity-Aware Zero Skipping for Compute-In-Memory Circuits

MEMORY CELL WITH BURIED POWER GRID, AND METHOD OF FABRICATING SAME

METHOD AND SYSTEM TO BALANCE GROUND BOUNCE

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...

LATCH CIRCUITS AND METHODS FOR OPERATING THE SAME

HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL

FLY SHARED BIT LINE ON 4-CPP STATIC RANDOM ACCESS MEMORY (SRAM) CEL...

SIGNED EXTENSION CARRY-LOOK-AHEAD FOR ACCUMULATOR WITH BIT WIDTH DI...

COMPUTE IN MEMORY

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

MEMORY DEVICES WITH REDUCED BIT LINE CAPACITANCE AND METHODS OF MAN...

MEMORY DEVICE INCLUDING DUAL CONTROL CIRCUITS