Hidenori Nomura

Person

Kasugai, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Word line multi-selection circuit for a memory device
- Patent number 5,909,407
- Issue date Jun 1, 1999
- Fujitsu Limited
- Yasuhiro Yamamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,619,465
- Issue date Apr 8, 1997
- Fujitsu Limited
- Hidenori Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,508,965
- Issue date Apr 16, 1996
- Fujitsu Limited
- Hidenori Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Wafer-scale semiconductor integrated circuit device and method of f...
- Patent number 5,349,219
- Issue date Sep 20, 1994
- Fujitsu Limited
- Toshiaki Murao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage reducing circuit
- Patent number 5,309,040
- Issue date May 3, 1994
- Fujitsu Limited
- Tomio Nakano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device having improved controlling function fo...
- Patent number 5,278,788
- Issue date Jan 11, 1994
- Fujitsu Limited
- Hidenori Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having a plurality of selectively activ...
- Patent number 5,239,508
- Issue date Aug 24, 1993
- Fujitsu Limited
- Hidenori Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Data amplifying system in semiconductor memory device
- Patent number 5,222,041
- Issue date Jun 22, 1993
- Fujitsu VLSI Limited
- Miki Nishimori
- G11 - INFORMATION STORAGE
Information Patent Grant
Wiring structure in a wafer-scale integrated circuit
- Patent number 5,032,889
- Issue date Jul 16, 1991
- Fujitsu Limited
- Toshiaki Murao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory having improved refresh timing
- Patent number 4,985,868
- Issue date Jan 15, 1991
- Fujitsu Limited
- Tomio Nakano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having data bus reset circuits
- Patent number 4,870,617
- Issue date Sep 26, 1989
- Fujitsu Limited
- Masao Nakano
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having data bus reset circuit
- Patent number 4,821,232
- Issue date Apr 11, 1989
- Fujitsu Limited
- Masao Nakano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device employing address multiplexing
- Patent number 4,807,192
- Issue date Feb 21, 1989
- Fujitsu Limited
- Masao Nakano
- G11 - INFORMATION STORAGE
Information Patent Grant
Transfer gate circuit protected from latch up
- Patent number 4,806,795
- Issue date Feb 21, 1989
- Fujitsu Limited
- Masao Nakano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device having a CMOS sense amplifier
- Patent number 4,799,197
- Issue date Jan 17, 1989
- Fujitsu Limited
- Yukinori Kodama
- G11 - INFORMATION STORAGE

Hidenori Nomura

Person

Patents Grantslast 30 patents

Word line multi-selection circuit for a memory device

Semiconductor memory device

Semiconductor memory device

Wafer-scale semiconductor integrated circuit device and method of f...

Voltage reducing circuit

Semiconductor memory device having improved controlling function fo...

Semiconductor memory device having a plurality of selectively activ...

Data amplifying system in semiconductor memory device

Wiring structure in a wafer-scale integrated circuit

Dynamic random access memory having improved refresh timing

Semiconductor memory device having data bus reset circuits

Semiconductor memory device having data bus reset circuit

Memory device employing address multiplexing

Transfer gate circuit protected from latch up

Semiconductor memory device having a CMOS sense amplifier