Hideo Fujiwara

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Kyoto, JP

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with design for testability and method for desig...
- Patent number 6,735,730
- Issue date May 11, 2004
- Semiconductor Technology Academic Research Center
- Hideo Fujiwara
- G01 - MEASURING TESTING
Information Patent Grant
Testable integrated circuit, integrated circuit design-for-testabil...
- Patent number 6,334,200
- Issue date Dec 25, 2001
- Semiconductor Technology Academic Research Center
- Hideo Fujiwara
- G01 - MEASURING TESTING
Information Patent Grant
Method of design for testability and method of test sequence genera...
- Patent number 6,292,915
- Issue date Sep 18, 2001
- Matsushita Electric Industrial Co., Ltd.
- Toshinori Hosokawa
- G01 - MEASURING TESTING