Method of design for testability and method of test sequence generation

Abstract

The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation. For the timeframe expanded combinational circuit, test patterns for multiple stuck-at faults are generated, the test patterns are transformed into test sequences on the basis of data on timeframes including primary inputs and pseudo-primary inputs, and the test sequences are transformed into scanning test sequences in view of a scan shift operation.

Description

BACKGROUND OF THE INVENTION

The present invention relates to design for testability and test sequence generation for integrated circuits (LSIs). More particularly, it relates to techniques to design for testability for an RTL circuit, that is, an integrated circuit designed at register transfer level (RTL).

A typical example of the conventional method of design for testability includes scan design. In the scan design, a flip-flop (FF) included in a logically designed LSI is replaced with a scan FF which can be externally directly controlled (scanned in) and observed (scanned out), so that a problem of a sequential circuit can be simplified into a problem of test pattern generation of a combinational circuit. Thus, test sequences can be easily generated (“Digital Systems Testing and Testable DESIGN, Chapter 9, Design For Testability”, 1990, published by Computer Science Press).

The conventional scan design includes full scan design in which all FFs are replaced with scan FFs and partial scan design in which merely FFs difficult to observe and control are replaced with scan FFs so as to overcome problems such as increase in hardware overhead occurring in the full scan design, both of which are executed mainly at gate level.

However, according to the conventional partial scan design at gate level, an operation timing of a gate level circuit generated through the logic synthesis can be harmfully affected by the scan design, so that a normal operation cannot be guaranteed. Therefore, re-design of the circuit is required, which can cause a problem that the design takes a long period of time.

As a countermeasure, partial scan design at register transfer level (RTL) with higher abstraction than the gate level is recently proposed.

For example, in an integrated circuit designed at RTL (i.e., an RTL circuit), registers to be made scannable (hereinafter referred to as scannable registers) are selected by using a testability measure or the like within a specified range of scan ratio (1995, ASPDAC (Asia and South Pacific Design Automation Conference), pp. 209-216, “Design For Testability Using Register Transfer level Partial Scan Selection”).

However, in the partial scan design at RTL, it is difficult to achieve high fault coverage at RTL. Specifically, in the RTL partial scan design, the fault coverage is to be increased as far as possible within the specified range of scan ratio, and therefore, it is necessary to repeat a series of procedures of selection of registers to replace with scan registers, logic synthesis, insertion of a scan path and test sequence generation until high fault coverage is achieved. Accordingly, the entire scan design requires a long period of time, resulting in disadvantageously increasing a cost for the design for testability.

SUMMARY OF THE INVENTION

The present invention provides a method of design for testability for modifying design of an integrated circuit at RTL so as to attain testability, by which high fault coverage can be guaranteed at RTL.

Also, the invention provides a method of test sequence generation for easily generating test sequences for a circuit having an easily testable circuit structure such as an RTL circuit whose design is modified to be easily testable by the method of design for testability.

Specifically, the method of design for testability of this invention for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprises a first step of specifying an easily testable circuit structure; and a second step of selecting scannable registers among registers included in the RTL circuit so that the RTL circuit in test has the easily testable circuit structure specified in the first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

According to the method of design for testability, scannable registers are selected so that the RTL circuit has the easily testable circuit structure specified in the first step. Therefore, high fault coverage can be guaranteed in upper stage of design. Furthermore, since the design for testability is performed at RTL, re-design can be largely avoided, and time required for the design of an LSI can be shortened as compared with time conventionally required.

Also, the method of test sequence generation, of this invention, for an RTL circuit, that is, an integrated circuit designed at register transfer level, the RTL circuit having an acyclic structure or having a structure in which scannable registers are selected and an acyclic structure is attained in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprises a first step of converting the RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit; a second step of generating test patterns for the timeframe expanded combinational circuit generated in the first step; and a third step of transforming the test patterns generated in the second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of the timeframe expanded combinational circuit generated in the first step.

According to the method of test sequence generation, the RTL circuit is converted, in the first step, into the gate level timeframe expanded combinational circuit for which test patterns can be easily generated, the test patterns for a combinational circuit are generated for the timeframe expanded combinational circuit in the second step, and the test patterns are transformed into test sequences for a scannable sequential circuit in the third step. In this manner, the test sequences for the sequential circuit can be easily generated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart for showing procedures in a method of design for testability according to a first embodiment of the invention;

FIG. 2 is a diagram for illustrating classification in structures of synchronous sequential circuits;

FIG. 3 is a directed graph for showing an example of an RTL circuit applicable to the method of design for testability of the first embodiment;

FIG. 4 is a directed graph for showing selection of scannable registers in the RTL circuit of FIG. 3 in the case where an acyclic structure is specified as an easily testable circuit structure;

FIG. 5 is a directed graph for showing selection of scannable registers in the RTL circuit of FIG. 3 in the case where a one-fold line-up structure is specified as the easily testable circuit structure;

FIG. 6 is a directed graph for showing selection of scannable registers in the RTL circuit of FIG. 3 in the case where a structure having combinational test pattern generation complexity (i.e., a balanced structure) is specified as the easily testable circuit structure;

FIG. 7 is a flowchart for showing procedures in a method of design for testability according to a second embodiment of the invention;

FIG. 8 is a directed graph for showing an example of an RTL circuit applicable to the method of design for testability of the second embodiment;

FIG. 9 is a directed graph obtained from the RTL circuit of FIG. 8 in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input;

FIG. 10 is a flowchart for showing procedures in a method of test sequence generation according to a third embodiment of the invention;

FIG. 11 is a flowchart for showing detailed procedures of an RTL timeframe expanding step S 20 in the method of test sequence generation of the third embodiment of FIG. 10 ;

FIG. 12 is a directed graph for showing an example of an RTL circuit applicable to the method of test sequence generation of the third embodiment;

FIG. 13 is a diagram resulting from timeframe expansion with respect to a pseudo-primary output PPO 1 in the RTL circuit of FIG. 12 ;

FIG. 14 is a diagram resulting from the timeframe expansion with a primary output PO 1 disposed in a timeframe 5 in addition to the timeframe expansion of FIG. 13 ;

FIG. 15 is a diagram resulting from the timeframe expansion with the primary output PO 1 disposed in a timeframe 4 in addition to the timeframe expansion of FIG. 13 ;

FIG. 16 is a diagram resulting from the timeframe expansion of the RTL circuit of FIG. 12 ;

FIG. 17 is a directed graph of a gate level circuit generated through logic synthesis of the RTL circuit of FIG. 12 ;

FIG. 18 is a diagram of a timeframe expanded combinational circuit generated from the RTL circuit of FIG. 12 on the basis of the timeframe expanded RTL circuit of FIG. 16 and the gate level circuit of FIG. 17 ;

FIG. 19 is a diagram for showing the timeframe expansion of the RTL circuit of FIG. 12 obtained when the primary output PO 1 is disposed in a timeframe 5 ;

FIG. 20 is another diagram for showing the timeframe expansion of the RTL circuit of FIG. 12 obtained when the primary output PO 1 is disposed in a timeframe 4 ;

FIG. 21 is a flowchart for showing procedures in a method of test sequence generation according to a fourth embodiment of the invention;

FIG. 22 is a directed graph for showing an example of an RTL circuit applicable to the method of test sequence generation of the fourth embodiment;

FIG. 23 is a directed graph resulting from grouping of combinational facilities in the RTL circuit of FIG. 22 ;

FIG. 24 is a diagram resulting from the timeframe expansion of the RTL circuit of FIG. 23 ;

FIG. 25 is a diagram of a timeframe expanded combinational circuit generated from the RTL circuit of FIG. 22 on the basis of the timeframe expanded RTL circuit of FIG. 24 ;

FIG. 26 is a flowchart for showing procedures in a method of test sequence generation according to a fifth embodiment of the invention;

FIG. 27 is a directed graph for showing an example of an RTL circuit applicable to a method of test sequence generation of a sixth embodiment;

FIG. 28 is a directed graph resulting from assuming scannable registers as pseudo-primary inputs and pseudo-primary outputs in the RTL circuit of FIG. 27 ;

FIG. 29 is a diagram for showing timeframe expansion according to the sixth embodiment on the RTL circuit of FIG. 28 ;

FIG. 30 is a diagram resulting from the timeframe expansion of the sixth embodiment on the RTL circuit of FIG. 28 ;

FIG. 31 is a directed graph for showing an example of an RTL circuit applicable to a method of test sequence generation according to a seventh embodiment of the invention;

FIG. 32 is a diagram for showing timeframe expansion of the seventh embodiment on the RTL circuit of FIG. 31 ;

FIGS. 33 ( a ) and 33 ( b ) are diagrams resulting from the timeframe expansion of the seventh embodiment on the RTL circuit of FIG. 31 , wherein FIG. 33 ( a ) shows a result obtained when a primary output PO 2 is disposed in a timeframe 4 and FIG. 33 ( b ) shows a result obtained when the primary output PO 2 is disposed in a timeframe 3 ;

FIGS. 34 ( a ) and 34 ( b ) are diagrams for showing results of conversion of the timeframe expanded RTL circuits of FIGS. 33 ( a ) and 33 ( b ) into gate level circuits, wherein FIG. 34 ( a ) shows the result obtained from FIG. 33 ( a ) and FIG. 34 ( b ) shows the result obtained from FIG. 33 ( b );

FIG. 35 is a schematic diagram for showing an example of an RTL circuit applicable to a method of design for testability according to an eighth embodiment of the invention;

FIGS. 36 ( a ) through 36 ( c ) are directed graphs for showing structures of blocks in the RTL circuit of FIG. 35 , wherein FIG. 36 ( a ) shows the structure of a block A, FIG. 36 ( b ) shows the structure of a block B and FIG. 36 ( c ) shows the structure of a block C;

FIG. 37 is a directed graph for showing an example of an RTL circuit applicable to a method of design for testability according to a ninth embodiment of the invention;

FIG. 38 is a directed graph resulting from the design for testability of the ninth embodiment on the RTL circuit of FIG. 37 ;

FIG. 39 is a directed graph for showing an example of an RTL circuit applicable to a method of design for testability according to a tenth embodiment of the invention; and

FIG. 40 is a directed graph resulting from the design for testability of the tenth embodiment on the RTL circuit of FIG. 39 .

DETAILED DESCRIPTION OF THE INVENTION

(Embodiment 1)

FIG. 1 is a flowchart for showing procedures in a method of design for testability according to a first embodiment of the invention. As is shown in FIG. 1 , in step S 11 , an easily testable circuit structure is specified; in step S 12 , a directed graph is generated on the basis of RTL design data of an RTL circuit, that is, an integrated circuit designed at register transfer level (RTL); and in step S 13 , registers to be replaced with scan registers (namely, scannable registers) are selected in the directed graph generated in step S 12 so that the RTL circuit can attain the easily testable circuit structure specified in step S 11 .

In step S 11 , an acyclic structure, an n-fold line-up structure (wherein n is a natural number) or a structure with combinational test pattern generation complexity is specified as the easily testable circuit structure.

An acyclic structure means a circuit structure including no feedback loops. An n-fold line-up structure means a circuit structure in which paths between an arbitrary pair of a register of the circuit and a primary output or a pseudo-primary output have n or less sequential depths. A circuit having the n-fold line-up structure has a characteristic that each of the numbers of timeframes including each register is limited to n or less in timeframe expansion with respect to the arbitrary primary or pseudo-primary output. Also, a structure with combinational test pattern generation complexity means a structure with complexity applicable to a test pattern generation algorithm for a combinational circuit.

FIG. 2 is a diagram for showing classification in structures of synchronous sequential circuits. As is shown in FIG. 2 , the acyclic structure includes the n-fold line-up structure, and the n-fold line-up structure includes the structure with combinational test pattern generation complexity.

Furthermore, in the directed graph generated in step S 12 , facilities such as a combinational facility and a register are expressed as nodes and data transfer between the nodes is expressed as an edge. With regard to an RTL circuit including a finite state machine, a directed graph is generated after the entire RTL circuit is expressed by connections among registers and combinational facilities by logically synthesizing the finite state machine alone.

In step S 13 , scannable registers are selected so that the RTL circuit has the easily testable circuit structure specified in step S 11 in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

Now, the method of design for testability of this embodiment will be described by exemplifying a specific circuit with reference to FIGS. 3 through 6 .

FIG. 3 shows a directed graph for showing an example of the RTL circuit applicable to the method of design for testability of this embodiment, generated on the basis of RTL design data in step S 12 . In FIG. 3 , A through K indicate combinational facilities, reg 1 through reg 9 indicate registers, PI 1 and PI 2 indicate primary inputs, and PO 1 and PO 2 indicate primary outputs. The directed graph as is shown in FIG. 3 can be expressed as a chart or expressed by a hardware description language such as Verilog-HDL in the actual design for testability.

FIG. 4 is a directed graph for showing selection of scannable registers in step S 13 about the RTL circuit of FIG. 3 in the case where the acyclic structure is specified as the easily testable circuit structure in step S 11 . As is shown in FIG. 4 , the original directed graph includes three feedback loops: a loop 1 consisting of the registers reg 1 , reg 2 and reg 6 and the combinational facilities A, B and F; a loop 2 consisting of the registers reg 1 , reg 2 and reg 8 and the combinational facilities A, B and H; and a loop 3 consisting of the register reg 4 and the combinational facility D. Since both the loop 1 and the loop 2 include the registers reg 1 and reg 2 , the loops 1 and 2 can be broken by replacing either the register reg 1 or reg 2 with a scan register. Also, the loop 3 can be broken by replacing the register reg 4 with a scan register. Therefore, as is shown in FIG. 4 , the hatched registers reg 2 and reg 4 are selected as the scannable registers.

FIG. 5 is a directed graph for showing selection of scannable registers in step S 13 about the RTL circuit of FIG. 3 in the case where a one-fold line-up structure is specified as the easily testable structure in step S 11 . A one-fold line-up structure is the n-fold line-up structure when n=1, namely, a structure in which paths between a given register and a given primary output or pseudo-primary output have one sort of sequential depth. In other words, in a one-fold line-up structure, paths between one register and a given primary output or pseudo-primary output do not pass through this register and the paths have merely one sort of the number of registers.

As is shown in FIG. 5 , in the original directed graph, the registers reg 1 , reg 2 , reg 4 , reg 6 and reg 8 have paths passing therethrough, and paths between the register reg 3 and the primary output PO 1 have two sorts of the number of the registers (namely, two registers and one register). Therefore, the original directed graph does not have the one-fold line-up structure. At this point, when the registers reg 2 and reg 4 are replaced with scan registers as is shown in FIG. 5 , none of the registers has a path passing therethrough, and when the register reg 3 is replaced with a scan register, the paths between the each register and the primary outputs or pseudo-primary outputs have one sort of the number of registers. Thus, the one-fold line-up structure can be attained. Accordingly, the registers reg 2 , reg 3 and reg 4 hatched in FIG. 5 are selected as the scannable registers.

FIG. 6 is a directed graph for showing selection of scannable registers in step S 13 in the RTL circuit of FIG. 3 in the case where the structure with combinational test pattern generation complexity (a balanced structure) is specified as the easily testable circuit structure in step S 11 . In FIG. 6 , there is more than one sort of the number of registers in paths between the primary input PI 1 and the primary output PO 1 , and there is more than one sort of the number of registers in paths between the primary input PI 2 and the primary output PO 2 . Also, there is more than one sort of the number of registers in paths between the primary input PI 2 and the primary output PO 1 . Therefore, the circuit can attain the balanced structure by replacing the registers reg 2 , reg 4 and reg 7 with scan registers. Accordingly, as is shown in FIG. 6 , the hatched registers reg 2 , reg 4 and reg 7 are selected as the scannable registers.

In this manner, the scannable registers are selected so that the RTL circuit has the easily testable circuit structure, such as the acyclic structure, the n-fold line-up structure and the structure with combinational test pattern generation complexity, in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input. Accordingly, high fault coverage can be guaranteed in upper stage of design. Furthermore, since the scannable registers are already selected in performing the logic synthesis, an operation timing of a gate level circuit generated through the logic synthesis cannot be affected by the scan design performed thereafter. Thus, re-design can be largely avoided.

(Embodiment 2)

FIG. 7 is a flowchart for showing procedures in a method of design for testability according to a second embodiment of the invention. The method of design for testability of this embodiment shown in FIG. 7 includes, in addition to the procedures of the method of design for testability of the first embodiment shown in FIG. 1 , step S 14 of additionally selecting scannable registers.

In step S 14 , in the RTL circuit in which the scannable registers are selected in step S 13 , scannable registers are additionally selected so that each path between one pseudo-primary input and primary outputs or pseudo-primary outputs contains the same number of registers in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

FIG. 8 is a directed graph for showing an example of an RTL circuit applicable to the method of design for testability of this embodiment, generated on the basis of RTL design data in step S 12 . In FIG. 8 , A through D indicate combinational facilities, reg 1 through reg 4 indicate registers, PI 1 and PI 2 indicate primary inputs and PO 1 indicates a primary output. In the directed graph of FIG. 8 , the acyclic structure is assumed to be specified as the easily testable circuit structure in step S 11 . Since the original directed graph includes a loop consisting of the registers reg 1 and reg 3 and the combinational facilities B and C, the hatched register reg 1 is selected as the scannable register so as to break this loop.

FIG. 9 is a directed graph obtained by assuming the normal data input of the register reg 1 , which is selected as the scannable register in the RTL circuit of FIG. 8 , as a pseudo-primary output PPO 1 and the data output thereof as a pseudo-primary input PPI 1 . In FIG. 9 , paths between the pseudo-primary input PPI 1 and the primary input PO 1 contain two sorts of the number of registers (namely, one register and two registers). Therefore, the hatched register reg 4 is additionally selected as the scannable register in step S 14 , so that each path contains the same number of registers.

In this manner, when the scannable registers are additionally selected so that each path from one pseudo-primary input to primary outputs or pseudo-primary outputs contains the same number of registers in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, a shift operation can be limited in scanning test sequences for a given fault. As a result, the number of test sequences can be reduced.

(Embodiment 3)

In a third embodiment of the invention, a method of test sequence generation for a sequential circuit will be described. The method of test sequence generation of this embodiment is applicable to an RTL circuit in which scannable registers are selected by the method of design for testability of the first or second embodiment. Furthermore, the method of test sequence generation of this embodiment is applicable also to an RTL circuit initially having the acyclic structure in test and an RTL circuit in which scannable registers are selected and the acyclic structure is attained in assuming a normal data input of the scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input in test.

FIG. 10 is a flowchart for showing procedures in the method of test sequence generation of the third embodiment. In FIG. 10 , in step S 20 , an applied RTL circuit is timeframe expanded, so as to generate a timeframe expanded RTL circuit, and data of timeframes including each of primary outputs and pseudo-primary outputs are stored; in step S 31 , the RTL circuit is logically synthesized to generate a gate level circuit; in step S 32 , the gate level circuit is timeframe expanded on the basis of data of the timeframes including each of primary outputs and pseudo-primary outputs stored in step S 20 , so as to generate a timeframe expanded gate level circuit, namely, a timeframe expanded combinational circuit, as a test sequence generating circuit, and data of timeframes including each of primary inputs and pseudo-primary inputs are stored; in step S 33 , test patterns for a combinational circuit for detecting multiple stuck-at faults are generated with regard to the timeframe expanded combinational circuit generated in step S 32 ; in step S 34 , the test patterns generated in step S 33 are transformed into test sequences for a sequential circuit on the basis of data of the timeframes including the primary inputs and pseudo-primary inputs stored in step S 32 ; and in step S 35 , the test sequences transformed in step S 34 are transformed into scanning test sequences in view of a scan shift operation.

First, procedures in step S 20 will be described with reference to FIGS. 11 through 20 .

FIG. 11 is a flowchart for showing detailed procedures of step S 20 in the method of test sequence generation of this embodiment. In the flowchart of FIG. 11 , in step S 21 , about each of primary outputs and pseudo-primary outputs, the maximum value of sequential depths to primary inputs or pseudo-primary inputs, namely, a maximum sequential depth, is obtained; in step S 22 , the primary outputs and pseudo-primary outputs are sorted in the descending order of their maximum sequential depths; in step S 23 , the number of timeframes in the timeframe expansion is set; and in steps S 24 through S 26 , the timeframe expansion is conducted about each of the primary outputs and pseudo-primary outputs in the sorted order obtained in step S 22 on the basis of a predetermined evaluation function.

FIG. 12 is a directed graph for showing an example of an RTL circuit applicable to the method of test sequence generation of this embodiment. In FIG. 12 , A through I indicate combinational facilities, reg 1 through reg 7 indicate registers, PI 1 through PI 3 indicate primary inputs, PPI 1 indicates a pseudo-primary input, PO 1 indicates a primary output and PPO 1 indicates a pseudo-primary output.

First, in step S 21 , the maximum sequential depths of the primary output PO 1 and the pseudo-primary output PPO 1 are obtained. With regard to the primary output PO 1 , a sequential depth to the primary input PI 1 is 2, a sequential depth to the primary input PI 2 is 2 and a sequential depth to the pseudo-primary input PPI 1 is 3, and hence, the maximum sequential depth of the primary output PO 1 is 3. Also, with regard to the pseudo-primary output PPO 1 , a sequential depth to the primary input PI 1 is 3, a sequential depth to the primary input PI 2 is 3 and a sequential depth to the pseudo-primary input PPI 1 is 4, and hence, the maximum sequential depth of the pseudo-primary output PPO 1 is 4.

Next, in step S 22 , the primary output PO 1 and the pseudo-primary output PPO 1 are sorted in the descending order of their maximum sequential depths. As a result, they are sorted in the order of the pseudo-primary output PPO 1 and the primary output PO 1 .

Then, in step S 23 , the number of timeframes in the timeframe expansion is set. The number of timeframes required for the timeframe expansion is given by adding 1 to the maximum value of the maximum sequential depths of each of primary outputs and pseudo-primary outputs. Therefore, a value obtained by adding 1 to the maximum sequential depth of the pseudo-primary output PPO 1 which is sorted in the lead, namely, 5 is set as the number of timeframes.

Thereafter, the RTL circuit is timeframe expanded in steps S 24 through S 26 . The timeframe expansion in this embodiment is conducted about each of the primary or pseudo-primary outputs in the sorted order obtained in step S 22 . Specifically, the timeframe expansion is conducted first about the pseudo-primary output PPO 1 , and then about the primary output PO 1 . In the timeframe expansion, it is determined on the basis of a predetermined evaluation function which timeframe includes the primary or pseudo-primary output.

In this embodiment, the total number of combinational facilities included in each timeframe is used as the evaluation function, and the timeframe expansion is conducted so as to make this evaluation function as small as possible. The number of gates of a test sequence generating circuit is substantially in proportion to the total number of combinational facilities included in each timeframe, and test sequences can be generated more easily when the number of gates of the test sequence generating circuit is smaller. Therefore, when the total number of combinational facilities included in each timeframe is used as the evaluation function for the timeframe expansion, test sequences can be more easily generated.

FIG. 13 is a diagram for showing a result of the timeframe expansion with respect to the pseudo-primary output PPO 1 . Since the maximum sequential depth of the pseudo-primary output PPO 1 is 4, the number of timeframes required for the timeframe expansion is 5, which is equal to the number of timeframes set in step S 23 . Therefore, the pseudo-primary output PPO 1 is inevitably determined to be disposed in a timeframe 5 .

Next, the timeframe expansion is conducted about the primary output PO 1 . Since the maximum sequential depth of the primary output PO 1 is 3, the number of timeframes required for the timeframe expansion is 4. Therefore, the primary output PO 1 is disposed in a timeframe 4 or 5 , and it is determined whether the primary output PO 1 is disposed in the timeframe 4 or in the timeframe 5 on the basis of the evaluation function.

FIG. 14 is a diagram obtained when the primary output PO 1 is disposed in the timeframe 5 . The number of combinational facilities concerning the timeframe expansion with respect to the pseudo-primary output PPO 1 is 10, and the number of combinational facilities concerning the timeframe expansion with respect to the primary output PO 1 is 7. Therefore, when none of the combinational facilities appears twice in each timeframe, the total number of combinational facilities included in the timeframes, that is, the value of the aforementioned evaluation function, is 17. In FIG. 14 , the combinational facility F appears twice in a timeframe 2 , and the combinational facility A appears twice in a timeframe 3 , and hence, the number of the combinational facilities appearing twice is 2. Therefore, the value of the evaluation function obtained by disposing the primary output PO 1 in the timeframe 5 is 15, which is obtained by subtracting the number of the combinational facilities appearing twice, i.e., 2, from the total number of the combinational facilities included in the timeframes, i.e., 17.

FIG. 15 is a diagram obtained when the primary output PO 1 is disposed in the timeframe 4 . In FIG. 15 , the combinational facility F appears twice in a timeframe 1 , the combinational facilities A, F and G respectively appear twice in the timeframe 2 , and the combinational facilities B and H respectively appear twice in the timeframe 3 . Therefore, the number of the combinational facilities appearing twice is 6. Accordingly, the value of the evaluation function obtained by disposing the primary output PO 1 in the timeframe 4 is 11, which is obtained by subtracting the number of the combinational facilities appearing twice, i.e., 6, from the total number of the combinational facilities included in the timeframes, i.e., 17.

As a result, the primary output PO 1 is determined to be disposed in the timeframe 4 . In this manner, the timeframe expansion of the RTL circuit of FIG. 12 results in a timeframe expanded RTL circuit as is shown in FIG. 16 . In step S 20 , the position of the pseudo-primary output PPO 1 is stored as the timeframe 5 , and the position of the primary output PO 1 is stored as the timeframe 4 .

Next, in step S 31 , the gate level circuit is generated through logic synthesis of the RTL circuit. FIG. 17 is a directed graph of the gate level circuit generated through the logic synthesis of the RTL circuit of FIG. 12 .

Then, in step S 32 , on the basis of the timeframe expanded RTL circuit obtained In step S 20 and the gate level circuit generated in step S 31 , the timeframe expanded gate level circuit for test sequence generation (i.e., the timeframe expanded combinational circuit) is generated. Specifically, each of the primary outputs and pseudo-primary outputs of the applied RTL circuit is disposed in the timeframes stored in step S 20 , and the timeframe expansion is conducted at gate level about the thus disposed primary outputs and pseudo-primary outputs on the basis of data of the gate level circuit generated in step S 31 , thereby generating the timeframe expanded combinational circuit. FIG. 18 is a diagram of the timeframe expanded combinational circuit generated in step S 32 on the basis of the timeframe expanded RTL circuit of FIG. 16 and the gate level circuit of FIG. 17 .

Next, in step S 33 , with regard to the timeframe expanded combinational circuit generated in step S 32 , multiple test patterns for a combinational circuit are generated. For example, with regard to the timeframe expanded combinational circuit of FIG. 18 , the following test patterns for detecting a fault are generated:

PI 1 ( 2 )=0 , PI 1 ( 3 )=1 , PI 2 ( 2 )=0 , PI 3 ( 4 )=1

PPI 1 ( 1 )=0 , PPI 1 ( 2 )=1

wherein each numeral in parentheses corresponds to the number of the timeframe. For example, “PPI 1 ( 1 )=0” means that a test pattern for the pseudo-primary input PPI 1 disposed in the timeframe 1 is “0”.

Next, in step S 34 , the test patterns generated in step S 33 are transformed into test sequences for a sequential circuit in accordance with the timeframes including each of primary inputs and pseudo-primary inputs. The test patterns for the timeframe expanded combinational circuit of FIG. 18 are transformed into the following test sequences (X means Don't Care):

PI 1 = X 01 XX, PI 2 = X 0 XXX, PI 3 = XXX 1 X

PPI 1 = 01 XXX

Furthermore, in step S 35 , the test sequences for the pseudo-primary input are transformed into scanning test sequences in view of a scan path shift operation. With regard to the timeframe expanded combinational circuit of FIG. 18 , the test sequence for the pseudo-primary input PPI 1 is transformed into a scanning test sequence.

In this manner, by using the total number of the combinational facilities included in each timeframe as the evaluation function, the RTL circuit is timeframe expanded with minimizing the evaluation function, and the timeframe expanded combinational circuit is thus generated. Accordingly, the size of the combinational circuit for test pattern generation can be made smaller, resulting in easily generating the test sequences.

In this embodiment, the total number of the combinational facilities in each timeframe is used as the evaluation function, but a sum of values weighted in accordance with the types of each combinational facility can be used as the evaluation function. Also, the total of the numbers of gates estimated for the combinational facilities in each timeframe can be used as the evaluation function.

Also, in the RTL timeframe expansion in step S 20 , the timeframe including one primary or pseudo-primary output can be determined without changing the timeframe including another primary or pseudo-primary output already determined with optimizing the evaluation function. Alternatively, the timeframe including another primary or pseudo-primary output already determined can be changed so as to optimize the evaluation function.

The evaluation function used in the RTL timeframe expansion is not limited to the total number of the combinational facilities included in each timeframe.

As another example of the evaluation function, the number of timeframes including a pseudo-primary input or a pseudo-primary output can be used as follows: The number of timeframes including a pseudo-primary input or a pseudo-primary output corresponds to the number of times of the shift operation required in test sequences for detecting a given fault. Therefore, when this evaluation function has a smaller value, the number of times of the shift operation is decreased, resulting in decreasing the length of test sequences. Accordingly, when the timeframe expansion is conducted so as to make this evaluation function have a smaller value, the number of the resultant test sequences can be reduced.

FIGS. 19 and 20 are diagrams for showing results of the timeframe expansion of the RTL circuit of FIG. 12 , wherein FIG. 19 shows the result obtained by disposing the primary output PO 1 in the timeframe 5 and FIG. 20 shows the result obtained by disposing the primary output PO 1 in the timeframe 4 . As is shown in FIG. 19 , when the primary output PO 1 is disposed in the timeframe 5 , the number of the timeframes including the pseudo-primary input PPI 1 or the pseudo-primary output PPO 1 is 4 (i.e., the timeframes 1 , 2 , 3 and 5 ), and hence, the evaluation function has a value of 4. On the other hand, as is shown in FIG. 20 , when the primary output PO 1 is disposed in the timeframe 4 , the number of the timeframes including the pseudo-primary input PPI 1 or the pseudo-primary output PPO 1 is 3 (i.e., the timeframes 1 , 2 and 5 ), and hence, the evaluation function has a value of 3.

Accordingly, the primary output PO 1 is determined to be disposed in the timeframe 4 so as to make the evaluation function smaller. Also in this case, the timeframe expansion of the RTL circuit of FIG. 12 results in as is shown in FIG. 16 .

In this manner, by timeframe expanding the RTL circuit on the basis of the predetermined evaluation function, the timeframe expanded combinational circuit for test sequence generation is generated, so that the test sequences can be easily generated or the number of the test sequences can be reduced.

(Embodiment 4)

In a fourth embodiment of the invention, similarly to the third embodiment, description will be give on a method of test sequence generation for an RTL circuit having the acyclic structure in test or an RTL circuit in which scannable registers are determined and the acyclic structure can be attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

FIG. 21 is a flowchart for showing procedures in the method of test sequence generation of the fourth embodiment. As is shown in FIG. 21 , the method of test sequence generation of this embodiment includes the same steps S 33 through S 35 as the method of test sequence generation of the third embodiment.

In step S 40 , in an applied RTL circuit, combinational facilities having none of registers, primary inputs and primary outputs on a path therebetween are grouped; in step S 41 , the RTL circuit is timeframe expanded with the grouped combinational facilities obtained in step S 40 regarded as one combinational facility, so as to generate a timeframe expanded RTL circuit; in step S 42 , logic synthesis is conducted by using the grouped combinational facilities obtained in step S 40 as one unit, so as to generated a gate level circuit; and in step S 43 , a timeframe expanded combinational circuit for test sequence generation is generated on the basis of the timeframe expanded RTL circuit generated in step S 40 and the gate level circuit of each group generated in step S 42 , and timeframes including each of primary inputs and pseudo-primary inputs are stored.

FIG. 22 is a directed graph for showing an example of the RTL circuit applicable to the method of test sequence generation of this embodiment. In FIG. 22 , A through I indicate combinational facilities, reg 1 through reg 6 indicate registers, PI 1 indicates a primary input, PPI 1 indicates a pseudo-primary input, PO 1 indicates a primary output and PPO 1 indicates a pseudo-primary output.

First, in step S 40 , the combinational facilities A through I are divided into groups. In FIG. 22 , the combinational facilities A and B together form a group P 1 , the combinational facilities C, D, E and F together form a group P 2 , and the combinational facilities H, G and I respectively form groups P 3 , P 4 and P 5 . FIG. 23 shows the result of the grouping of each combinational facility in step S 40 .

Next, in step S 41 , the RTL circuit of FIG. 23 is timeframe expanded in the same manner as in step S 20 of the third embodiment. FIG. 24 is a diagram of the timeframe expanded RTL circuit resulting from the timeframe expansion in step S 41 .

Then, in step S 42 , by using each of the groups P 1 through P 5 obtained in step S 40 as one unit, the logic synthesis is conducted, so as to generate gate level combinational circuits respectively corresponding to the groups P 1 through P 5 . In step S 43 , the gate level combinational circuits generated in step S 42 are allocated to each of the groups P 1 through P 5 of the timeframe expanded RTL circuit generated in step S 41 of FIG. 24 , so that a timeframe expanded combinational circuit as is shown in FIG. 25 can be generated as the test sequence generating circuit. The procedures thereafter are the same as those described in the third embodiment.

(Embodiment 5)

In a fifth embodiment of the invention, similarly to the third and fourth embodiments, description will be given on a method of test sequence generation for an RTL circuit having the acyclic structure in test or an RTL circuit in which scannable registers are determined and the acyclic structure can be attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

FIG. 26 is a flowchart for showing procedures in the method of test sequence generation of the fifth embodiment. As is shown in FIG. 26 , the method of test sequence generation of this embodiment includes the same steps S 33 through S 35 as the methods of test sequence generation of the third and fourth embodiments.

In step S 51 , a gate level circuit is generated by logically synthesizing an applied RTL circuit; and in step S 52 , the gate level circuit generated in step S 51 is timeframe expanded, so as to generate a timeframe expanded combinational circuit for test sequence generation, and timeframes including each of the primary inputs and pseudo-primary inputs are stored.

The gate level timeframe expansion in step S 52 is conducted on the basis of a predetermined evaluation function as in the RTL timeframe expansion in step S 20 of the third embodiment.

For example, by using the total number of gates included in each timeframe as the evaluation function, and the timeframe expanded combinational circuit is generated through the gate level timeframe expansion with making this evaluation function as small as possible. Thus, the size of the combinational circuit for generating test patterns can be minimized, resulting in easily generating test sequences. Alternatively, when the number of timeframes including a pseudo-primary input or a pseudo-primary output is used as the evaluation function, the number of the resultant test sequences can be reduced.

(Embodiment 6)

In a sixth embodiment of the invention, similarly to the third and fourth embodiments, description will be give on a method of test sequence generation for an RTL circuit having the acyclic structure in test or an RTL circuit in which scannable registers are determined and the acyclic structure can be attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input. In this embodiment, an evaluation function different from that of the third embodiment is used for the timeframe expansion.

In this embodiment, an evaluation function for minimizing the number of timeframes including each pseudo-primary output is used. Specifically, the sum of the total number of timeframes including each pseudo-primary input and the total number of timeframes including each pseudo-primary output is used as the evaluation function. However, when the pseudo-primary input corresponding to a register is included in a timeframe following a timeframe including the pseudo-primary output corresponding to the register, the number of such registers is subtracted from the value of the evaluation function. At this point, a timeframe following the last timeframe corresponds to the first timeframe.

Furthermore, when the test patterns are transformed into test sequences with one scan path formed by using scan FFs composing registers corresponding to each pseudo-primary output disposed in one timeframe and scan FFs composing registers corresponding to each pseudo-primary input disposed in the following timeframe, the length of the test sequences can be shortened.

FIG. 27 is a directed graph for showing an example of an RTL circuit applicable to the method of test sequence generation of this embodiment. In FIG. 27 , A through G indicate combinational facilities, reg 1 through reg 5 indicate registers, PI 1 and PI 2 indicate primary inputs, and PO 1 and PO 2 indicate primary outputs. The RTL circuit of FIG. 27 includes two feedback loops, and the registers reg 4 and reg 5 are selected as the scannable registers, so as to break the two feedback loops and attain the acyclic structure.

FIG. 28 is a directed graph obtained in assuming each of the scannable registers with a pseudo-primary input and a pseudo-primary output in the RTL circuit of FIG. 27 . In FIG. 28 , the register reg 4 is assumed as a pseudo-primary input PPIr 4 and a pseudo-primary output PPOr 4 , and the register reg 5 is assumed as a pseudo-primary input PPIr 5 and a pseudo-primary output PPOr 5 .

FIG. 29 is a diagram resulting from the timeframe expansion of this embodiment on the RTL circuit of FIG. 28 . Since the RTL circuit of FIG. 28 has a sequential depth (i.e., the maximum value of the maximum sequential depths of each of the primary outputs and pseudo-primary outputs) of 3, the number of timeframes in the timeframe expansion is set at 4 as is shown in FIG. 29 . Then, the timeframe expansion is conducted first about the pseudo-primary output PPOr 4 having the largest maximum sequential depth.

Next, the timeframe expansion is conducted about the pseudo-primary output PPOr 5 having the maximum sequential depth of 1.

When the pseudo-primary output PPOr 5 is disposed in the timeframe 4 (as is shown as a case (i) of FIG. 29 ), the pseudo-primary input PPIr 4 is included in the timeframes 1 and 3 , the pseudo-primary input PPIr 5 is included in the timeframe 4 , and the pseudo-primary outputs PPOr 4 and PPOr 5 are both included in the timeframe 4 . In addition, with regard to the register reg 4 , the pseudo-primary output PPOr 4 is included in the timeframe 4 and the pseudo-primary input PPIr 4 is included in the timeframe 1 . Therefore, the evaluation function has a value of 4 (=3+2−1).

When the pseudo-primary output PPOr 5 is disposed in the timeframe 3 (as is shown as a case (ii) of FIG. 29 ), the pseudo-primary input PPIr 4 Is Included In the timeframes 1 and 2 , the pseudo-primary input PPIr 5 is included in the timeframe 3 , the pseudo-primary output PPOr 4 is included in the timeframe 4 , and the pseudo-primary output PPOr 5 is included in the timeframe 3 . In addition, with regard to the register reg 4 , the pseudo-primary output PPOr 4 is included In the timeframe 4 and the pseudo-primary input PPIr 4 is included in the timeframe 1 . Therefore, the evaluation function has a value of 4 (=3+2−1).

When the pseudo-primary output PPOr 5 is disposed in the timeframe 2 (as is shown as a case (iii) of FIG. 29 ), the pseudo-primary input PPIr 4 is included in the timeframe 1 , the pseudo-primary input PPIr 5 is included in the timeframe 2 , the pseudo-primary output PPOr 4 is included in the timeframe 4 , and the pseudo-primary output PPOr 5 is included in the timeframe 2 . In addition, with regard to the register reg 4 , the pseudo-primary output PPOr 4 is included in the timeframe 4 and the pseudo-primary input PPIr 4 is included in the timeframe 1 . Therefore, the evaluation function has a value of 3 (=2+2−1).

Accordingly, the pseudo-primary output PPOr 5 is determined to be disposed in the timeframe 2 so as to minimize the value of the evaluation function. Similarly, the primary output PO 1 is determined to be disposed in the timeframe 1 , and the primary output PO 2 is determined to be disposed in the timeframe 3 .

As a result, a timeframe expanded RTL circuit as is shown in FIG. 30 is generated. In FIG. 30 , the pseudo-primary inputs and pseudo-primary outputs are disposed as follows: the timeframe 1 includes the pseudo-primary input PPIr 4 alone, the timeframe 2 includes the pseudo-primary input PPIr 5 and the pseudo-primary output PPOr 5 alone, the timeframe 3 includes the pseudo-primary input PPIr 5 alone, and the timeframe 4 includes the pseudo-primary output PPOr 4 alone.

In the timeframe expanded combinational circuit for test sequence generation generated on the basis of the timeframe expanded RTL circuit of FIG. 30 , the register reg 4 forms one scan path and the register reg 5 forms another scan path.

For example, it is assumed that the register reg 4 has a data width of 8 bits and the register reg 5 has a data width of 4 bits. In this case, the number of FFs composing the registers reg 4 and reg 5 is 12.

At this point, when two scan paths each including 6 scan FFs are simply formed and each scan path includes the scan FFs of both the registers reg 4 and reg 5 , a shift operation is required in the timeframes 1 , 2 and 3 , and hence, the length of a test sequence for a shift operation necessary for one test pattern is 18 (=6·3).

On the other hand, when the 8 scan FFs composing the register reg 4 together form one scan path and the 4 scan FFs composing the register reg 5 together form another scan path, the length of a test sequence for a shift operation necessary for one test pattern is 16 (=8+4·2).

In this manner, through the timeframe expansion by using the evaluation function for minimizing the number of timeframes including each pseudo-primary output, the number of the resultant test sequences can be reduced.

(Embodiment 7)

In a seventh embodiment of the invention, similarly to the third and fourth embodiments, description will be given on a method of test sequence generation for an RTL circuit having the acyclic structure in test or an RTL circuit in which scannable registers are determined and the acyclic structure can be attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input. In this embodiment, an evaluation function different from that of the third embodiment is used in the timeframe expansion.

In this embodiment, the total number of primary inputs included in each timeframe is used as the evaluation function. The timeframe expansion is conducted with maximizing the value of this evaluation function.

FIG. 31 is a directed graph for showing an example of an RTL circuit having the acyclic structure applicable to the method of test sequence generation of this embodiment. In FIG. 31 , A through F indicate combinational facilities, reg 1 through reg 4 indicate registers, PI 1 and PI 2 indicate primary inputs and PO 1 and PO 2 indicate primary outputs.

FIG. 32 is a diagram resulting from the timeframe expansion of this embodiment on the RTL circuit of FIG. 31 . Since the RTL circuit of FIG. 31 has a sequential depth (namely, the maximum value of the maximum sequential depths of each of primary outputs and pseudo-primary outputs) of 3, the number of timeframes in the timeframe expansion is set at 4 as is shown in FIG. 32 . Then, the timeframe expansion is conducted first about the primary output PO 1 having the largest maximum sequential depth.

Next, the timeframe expansion is conducted about the primary output PO 2 . When the primary output PO 2 is disposed in the timeframe 4 (as is shown as a case (i) of FIG. 32 ), the timeframe 1 includes the primary input PI 1 , the timeframe 2 includes the primary input PI 1 , and the timeframe 3 includes the primary inputs PI 1 and PI 2 , and hence, the evaluation function has a value of 4 (=1+1+2). On the other hand, when the primary output PO 2 is disposed in the timeframe 3 (as is shown as a case (ii) of FIG. 32 ), the timeframe 1 includes the primary input PI 1 and the timeframe 2 includes the primary inputs PI 1 and PI 2 , and hence, the evaluation function has a value of 3 (=1+2). Therefore, the primary output PO 2 is determined to be disposed in the timeframe 4 so as to maximize the value of the evaluation function.

FIGS. 33 ( a ) and 33 ( b ) are diagrams of timeframe expanded RTL circuits generated through the timeframe expansion of this embodiment on the RTL circuit of FIG. 31 , wherein the circuit of FIG. 33 ( a ) is obtained by disposing the primary output PO 2 in the timeframe 4 and the circuit of FIG. 33 ( b ) is obtained by disposing the primary output PO 2 in the timeframe 3 .

FIGS. 34 ( a ) and 34 ( b ) are diagrams of gate level circuits obtained from the timeframe expanded RTL circuits of FIGS. 33 ( a ) and 33 ( b ), wherein FIG. 34 ( a ) shows the circuit obtained from FIG. 33 ( a ) where the primary output PO 2 is disposed in the timeframe 4 and FIG. 34 ( b ) shows the circuit obtained from FIG. 33 ( b ) where the primary output PO 2 is disposed in the timeframe 3 . In FIGS. 34 ( a ) and 34 ( b ), the combinational facility A is replaced with one NOT gate ga, the combinational facility B is replaced with one NOT gate gb, the combinational facility C is replaced with one NAND gate gc, the combinational facility D is replaced with one NOT gate gd, the combinational facility E is replaced with one NOR gate ge, and the combinational facility F is replaced with one AND gate gf.

In the circuit of FIG. 34 ( a ), test patterns for detecting stuck at “0” fault at the output of the NAND gate gc are:

PI 1 ( 0 )=0, PI 1 ( 1 )=1, PI 1 ( 2 )=0, PI 2 ( 2 )=1

and by using the same test patterns, stuck at “1” fault at the output of the NOR gate ge can be also detected. On the other hand, in the circuit of FIG. 34 ( b ), test patterns for detecting stuck at “0” fault at the output of the NAND gate gc are:

PI 1 ( 0 )=0, PI 1 ( 1 )=1, PI 2 ( 1 )=1

According to these test patterns, one input of the AND gate gf is always “0” because PI 1 ( 1 )=1, and hence, the output of the AND gate gf is always “0”. Accordingly, stuck at “1” fault at the output of the NOR gate ge cannot be detected by using these test patterns.

In this manner, when the number of the primary inputs included in each timeframe is larger, the number of detectable faults by using one test pattern is larger, resulting in shortening the necessary length of a test pattern. Accordingly, through the timeframe expansion on the basis of the evaluation function of this embodiment, the length of the resultant test sequences can be shortened.

The evaluation functions described in the sixth and seventh embodiments can be used also in the case where the timeframe expansion is conducted at gate level as in the fifth embodiment.

(Embodiment 8)

In an eighth embodiment of the invention, a method of design for testability similar to that of the first embodiment is described, in which an RTL circuit is partitioned into plural blocks and scannable registers are selected in each block so that each block can attain an easily testable circuit structure.

FIG. 35 is a schematic diagram of an RTL circuit partitioned into plural blocks. The RTL circuit of FIG. 35 is partitioned into three blocks A, B and C. However, since the blocks A, B and C together form a feedback loop, the entire RTL circuit cannot be made easily testable simply by attaining an easily testable circuit structure in each block A, B and C. Since test sequences are generated with regard to the entire LSI, high fault coverage cannot be achieved unless the entire LSI is easily testable.

In each block, a register which can be reached, in a direction from the output to the input of the block, by passing merely through combinational facilities is selected as the scannable register. Then, scannable registers are selected so that each block can attain an easily testable circuit structure.

FIGS. 36 ( a ) through 36 ( c ) are directed graphs for showing the structures of each block of the RTL circuit of FIG. 35 , wherein FIG. 36 ( a ) shows the block A, FIG. 36 ( b ) shows the block B and FIG. 36 ( c ) shows the block C. In FIGS. 36 ( a ) through 36 ( c ), a through n indicate combinational facilities, reg 0 through reg 11 indicate registers, I 1 through I 7 indicate the inputs of the blocks, and O 1 through O 7 indicate the outputs of the blocks.

First, in each of the blocks A, B and C, a register which can be reached, in the direction from the output to the input of the block, by passing merely through the combinational facilities is selected as the scannable register. In the block A, the register reg 3 which can be directly reached from the output O 1 and the register reg 2 which can be reached from the output O 2 through the combinational facility c are selected as the scannable registers as is shown in FIG. 36 ( a ). In the block B, the register reg 6 which can be directly reached from the output O 3 , the register reg 7 which can be directly reached from the output O 4 and the register reg 8 which can be directly reached from the output O 5 are selected as the scannable registers as is shown in FIG. 36 ( b ). In the block C, the register reg 11 which can be directly reached from the outputs O 6 and O 7 is selected as the scannable register as is shown in FIG. 36 ( c ).

Then, scannable registers are selected so that each of the blocks A, B and C can attain an easily testable circuit structure. In this embodiment, the acyclic structure is specified as the easily testable circuit structure. In this case, the block A includes a loop which is not broken yet and consists of the registers reg 0 and reg 1 and the combinational facilities a, b and d. Therefore, the register reg 0 is selected as the scannable register in order to break this loop.

In this manner, the registers reg 0 , reg 2 , reg 3 , reg 6 , reg 7 , reg 8 and reg 11 hatched in FIGS. 36 ( a ) through 36 ( c ) are selected as the scannable registers. Thus, the entire RTL circuit is designed for testability, and high fault coverage can be guaranteed.

(Embodiment 9)

In a ninth embodiment of the invention, a method of design for testability similar to that of the first embodiment will be described. In this embodiment, a circuit structure different from that of the first embodiment is specified as the easily testable circuit structure.

In this embodiment, a circuit structure attaining multiplicity of n (wherein n is a natural number) as a result of the timeframe expansion is specified as the easily testable circuit structure. Specifically, the easily testable structure specified in this embodiment is a structure in which the types of register sets, each including a different number of registers not to be made scannable, is n or less in paths between a primary input or pseudo-primary input and a primary output or pseudo-primary output in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input. Such a circuit structure is herein designated as an “n-fold acyclic structure”. When n is 1, the n-fold acyclic structure is identical to the balanced structure.

FIG. 37 is a directed graph for showing an example of an RTL circuit applicable to the method of design for testability of this embodiment. In FIG. 37 , A through K indicate combinational facilities, reg 1 through reg 8 indicate registers, PI 1 and PI 2 indicate primary inputs and PO 1 and PO 2 indicate primary outputs.

Now, the RTL circuit of FIG. 37 is designed for testability by specifying a two-fold acyclic structure as the easily testable circuit structure. As is shown in FIG. 37 , the original directed graph includes three feedback loops: a loop consisting of the registers reg 1 and reg 5 and the combinational facilities A, B and F; a loop consisting of the registers reg 1 and reg 7 and the combinational facilities A, B and H; and a loop consisting of the register reg 3 and the combinational facility D. Therefore, in order to break these loops, the registers reg 1 and reg 3 are first selected as the scannable registers.

At this point, there are: a path including the one register reg 5 not to be made scannable; a path including the two registers reg 2 and reg 4 not to be made scannable; and a path including the three registers reg 2 , reg 6 and reg 8 not to be made scannable between the primary input PI 1 and the primary output PO 1 . Therefore, this RTL circuit has a three-fold acyclic structure. In order to make this circuit have the two-fold acyclic structure, the register reg 6 is selected as the scannable register.

As a result of the aforementioned procedures, the RTL circuit of FIG. 37 is designed for testability as is shown in FIG. 38 . The RTL circuit of FIG. 38 has the two-fold acyclic structure because the hatched registers reg 1 , reg 3 and reg 6 are selected as the scannable registers. When the RTL circuit of FIG. 38 is timeframe expanded, the resultant timeframe expanded circuit has multiplicity of 2, and hence, it is sufficient to consider a fault of up to two-fold in generating multiple fault test patterns. In this manner, by specifying the n-fold acyclic structure as the easily testable circuit structure, test sequences can be easily generated because the multiplicity to be considered in generating multiple fault test patterns can be limited to n.

(Embodiment 10)

In a tenth embodiment of the Invention, a method of design for testability similar to that of the first embodiment will be described. In this embodiment, a different circuit structure is specified as the easily testable circuit structure from that of the first embodiment.

In this embodiment, the easily testable structure is specified as a structure in which the number of stages of gates is n or less in each path from primary inputs or pseudo-primary inputs to primary outputs or pseudo-primary outputs in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input. As a premise, it Is necessary to estimate the number of stages of gates in each of combinational facilities of an RTL circuit.

FIG. 39 is a directed graph for showing an example of an RTL circuit applicable to the method of design for testability of this embodiment. In FIG. 39 , A through K indicate combinational facilities, reg 1 through reg 9 indicate registers, PI 1 and PI 2 indicate primary inputs, and PO 1 and PO 2 indicate primary outputs. As is shown in FIG. 39 , the number of stages of gates is estimated in each of the combinational facilities A through K. For example, in the combinational facility A, the numbers of stages of gates in two paths are estimated as 2 and 1, respectively.

Now, the RTL circuit of FIG. 39 is designed for testability by specifying, as the easily testable structure, a structure in which the number of stages of gates is 5 or less in each of paths from primary inputs or pseudo-primary inputs to primary outputs or pseudo-primary outputs.

First, in order to break a loop consisting of the register reg 4 and the combinational facility D, the register reg 4 is selected as the scannable register.

Next, in order to break a loop consisting of the registers reg 1 , reg 2 and reg 6 and the combinational facilities A, B and F, any of the registers reg 1 , reg 2 and reg 6 is selected as the scannable register.

When the register reg 1 is assumed to be selected as the scannable register, the following five paths have more than 5 stages of gates: a path from the register reg 1 to the primary output PO 1 (having 7 stages of gates); a path from the register reg 1 to the register reg 1 (having 7 stages of gates); a path from the register reg 1 to the primary output PO 2 (having 8 stages of gates); a path from the primary input PI 1 to the primary output PO 1 (having 6 stages of gates); and a path from the primary input PI 1 to the primary output PO 2 (having 7 stages of gates).

When the register reg 2 is assumed to be selected as the scannable register, the following three paths have more than 5 stages of gates: a path from the register reg 2 to the register reg 2 (having 7 stages of gates); a path from the primary input PI 1 to the primary output PO 1 (having 6 stages of gates); and a path from the register reg 4 to the register reg 2 (having 6 stages of gates).

When the register reg 6 is assumed to be selected as the scannable register, the following five paths have more than 5 stages of gates: a path from the register reg 6 to the register reg 6 (having 7 stages of gates); a path from the primary input PI 1 to the primary output PO 1 (having 6 stages of gates); a path from the primary input PI 1 to the primary output PO 2 (having 7 stages of gates); a path from the register reg 4 to the primary output PO 1 (having 10 stages of gates); and a path from the register reg 4 to the primary output PO 2 (having infinite stages of gates).

Accordingly, the register reg 2 is selected as the scannable register because the number of paths having more than 5 stages of gates is smallest when this register reg 2 is selected. By selecting the register reg 2 as the scannable register, a loop consisting of the registers reg 1 , reg 2 and reg 8 and the combinational facilities A, B and H can also be broken.

Next, any of the registers contained in the remaining paths having more than 5 stages of gates is selected as the scannable register, so that none of the paths has more than 5 stages of gates. As the paths having more than 5 stages of gates, there remain the path from the register reg 2 through the registers reg 6 and reg 1 to the register reg 2 (having 7 stages of gates), the path from the primary input PI 1 through the registers reg 3 and reg 5 to the primary output PO 1 (having 6 stages of gates), and the path from the register reg 4 through the registers reg 8 and reg 1 to the register reg 2 (having 6 stages of gates). Therefore, any of the registers reg 1 , reg 3 , reg 5 , reg 6 and reg 8 is selected as the scannable register.

When the register reg 1 is assumed to be selected as the scannable register, there remains merely one path having more than 5 stages of gates. When any of the other registers reg 3 , reg 5 , reg 6 and reg 8 is assumed to be selected as the scannable register, there remain two paths having more than 5 stages of gates. Therefore, the register reg 1 is selected as the scannable register.

Thus, merely the path from the primary input PI 1 through the registers reg 3 and reg 5 to the primary output PO 1 (having 6 stages of gates) remains as the path having more than 5 stages of gates. When any of the registers reg 3 and reg 5 is selected as the scannable register, no path in the RTL circuit has more than 5 stages of gates. At this point, the register reg 5 is selected as the scannable register.

As a result of the aforementioned procedures, the RTL circuit of FIG. 39 is designed for testability as is shown in FIG. 40 . In the RTL circuit of FIG. 40 , since the hatched registers reg 1 , reg 2 , reg 4 and reg 5 are selected as the scannable registers, each path from the primary inputs or pseudo-primary inputs to the primary outputs or pseudo-primary outputs has 5 or less stages of gates. When the RTL circuit of FIG. 40 is timeframe expanded, the number of stages of gates in each timeframe can probably be 5 or less. Test patterns for a combinational circuit are generally difficult to generate when the number of stages of gates is larger. Therefore, by specifying the structure in which each path from primary inputs or pseudo-primary inputs to primary outputs or pseudo-primary outputs has n or less stages of gates as the easily testable circuit structure as in this embodiment, test patterns can be easily generated.

Claims

1. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising:a first step of specifying as an easily testable circuit structure, an n-fold line-up structure in which paths between an arbitrary pair of a register of the circuit and a primary output or a pseudo-primary output have n or less sorts of sequential depths, where n is a natural number, and specifying a value of n; and a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

2. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising:a first step of specifying as an easily testable circuit structure, an n-fold acyclic structure in which paths from a primary or pseudo-primary input to a primary or pseudo-primary output contain n or less types of register sets, each said type of register set includes a different number of registers, where n is a natural number, and specifying a value of n; and a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

3. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising:a first step of specifying as an easily testable circuit structure, a structure in which each of paths from primary or pseudo-primary inputs to primary or pseudo-primary outputs contains n or less stages of gates, where n is 0 or a natural number, and specifying a value of n; and a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

4. A method of design for testability for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprising:a first step of specifying an easily testable circuit structure; and a second step of selecting scannable registers among registers included in said RTL circuit so that said RTL circuit in test has said easily testable circuit structure specified in said first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, wherein said second step includes: a first process for partitioning said RTL circuit into plural blocks; a second process for selecting, in each of said blocks, registers reachable in a direction from an output to an input of said block by passing merely through combinational facilities as said scannable registers; and a third process for selecting said scannable registers among said registers of said RTL circuit so that each block in test attains said easily testable circuit structure in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.

5. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising:a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit; a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step, wherein said first step includes: an RTL timeframe expanding process for timeframe expanding said RTL circuit on the basis of a predetermined evaluation function; a logic synthesizing process for converting said RTL circuit into a gate level circuit through logic synthesis; and a test sequence generation circuit generating process for generating said timeframe expanded combinational circuit on the basis of the timeframe expanded RTL circuit obtained in said RTL timeframe expanding process and the gate level circuit generating in said logic synthesizing process.

6. The method of test sequence generation of claim 5,wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a total number of combinational facilities included in each timeframe or the total of the numbers of gates estimated for the combinational facilities in each timeframe as said predetermined evaluation function, with minimizing said predetermined evaluation function.

7. The method of test sequence generation of claim 5,wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a number of timeframes including a pseudo-primary input or a pseudo-primary output as said predetermined evaluation function, with minimizing said predetermined evaluation function.

8. The method of test sequence generation of claim 5,wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using, as said predetermined evaluation function, a value obtained by subtracting a number of registers each of which the pseudo-primary input corresponding thereto is included in a timeframe following a timeframe including its corresponding pseudo-primary output from a sum of a total number of timeframes including each pseudo-primary input and a total number of timeframes including each pseudo-primary output, with minimizing said predetermined evaluation function.

9. The method of test sequence generation of claim 5,wherein, in said RTL timeframe expanding process, said RTL circuit is timeframe expanded by using a total number of primary inputs included in each timeframe as said predetermined evaluation function, with maximizing said predetermined evaluation function.

10. The method of test sequence generation of claim 5,wherein said RTL timeframe expanding process includes: a first process for obtaining a maximum sequential depth of each of primary outputs and pseudo-primary outputs of said RTL circuit; a second process for sorting said primary outputs and pseudo-primary outputs of said RTL circuit in a descending order of said maximum sequential depths thereof obtained in said first process; a third process for setting a value obtained by adding one to the maximum value of said maximum sequential depth obtained in said first process as a number of timeframes in timeframe expansion; and a fourth process for conducting timeframe expansion with respect to said primary outputs and pseudo-primary outputs in accordance with said predetermined evaluation function in the sorted order obtained in said second process.

11. The method of test sequence generation of claim 5,wherein said first step includes a pre-process for grouping, in said RTL circuit, combinational facilities containing none of registers, primary inputs and primary outputs in a path therebetween, in said RTL timeframe expanding process, the timeframe expansion is conducted with said combinational facilities grouped in said pre-process regarded as one combinational facility, and in said logic synthesizing process, the logic synthesis is conducted by using said combinational facilities grouped in said pre-process as one unit.

12. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising:a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit; a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step, wherein said first step includes: a logic synthesizing process for logically synthesizing said RTL circuit; and a gate level timeframe expanding process for generating said timeframe expanded combinational circuit through timeframe expansion of said gate level circuit generated in said logic synthesizing process on the basis of a predetermined evaluation function.

13. The method of test sequence generation of claim 12, wherein, in said gate level timeframe expanding process, said gate level circuit is timeframe expanded by using a total number of gates included in each timeframe as said predetermined evaluation function, with minimizing said predetermined evaluation function.

14. A method of test sequence generation for an RTL circuit, that is, an integrated circuit designed at register transfer level, said RTL circuit having an acyclic structure in test or having a structure in which scannable registers are selected and an acyclic structure is attained in test in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprising:a first step of converting said RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit; a second step of generating test patterns for said timeframe expanded combinational circuit generated in said first step; and a third step of transforming said test patterns generated in said second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of said timeframe expanded combinational circuit generated in said first step, wherein, in said third step, said test patterns are transformed into said test sequences with one scan path formed by using scan FFs composing a register corresponding to a pseudo-primary output included in one timeframe and scan FFs composing a register corresponding to a pseudo-primary input included in another following timeframe.