Hing-Yan To

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-die virtual probes (ODVP) for integrated circuitries
- Patent number 11,428,733
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Yanran Chen
- G01 - MEASURING TESTING
Information Patent Grant
Printed circuit board (PCB) modular design
- Patent number 10,860,776
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disparate clock domain synchronization
- Patent number 8,442,075
- Issue date May 14, 2013
- Intel Corporation
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Quad rate transmitter equalization
- Patent number 7,991,020
- Issue date Aug 2, 2011
- Intel Corporation
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,954,001
- Issue date May 31, 2011
- Intel Corporation
- Aaron K. Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Disparate clock domain synchronization
- Patent number 7,936,789
- Issue date May 3, 2011
- Intel Corporation
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock synchronization scheme for deskewing operations in a data int...
- Patent number 7,805,627
- Issue date Sep 28, 2010
- Intel Corporation
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-path clocking architecture
- Patent number 7,692,457
- Issue date Apr 6, 2010
- Intel Corporation
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating integrating receivers for source synchronous protocol
- Patent number 7,602,859
- Issue date Oct 13, 2009
- Intel Corporation
- Roger K. Cheng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for power efficient and scalable memory interface
- Patent number 7,459,938
- Issue date Dec 2, 2008
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for a configurable Vcc reference and Vss referenc...
- Patent number 7,446,572
- Issue date Nov 4, 2008
- Intel Corporation
- Hing Y. To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,401,246
- Issue date Jul 15, 2008
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular memory controller clocking architecture
- Patent number 7,388,795
- Issue date Jun 17, 2008
- Intel Corporation
- Hing To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimization of integrated circuit device I/O bus timing
- Patent number 7,334,148
- Issue date Feb 19, 2008
- Intel Corporation
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency normalization by balancing early and late clocks
- Patent number 7,324,403
- Issue date Jan 29, 2008
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining an optimal sampling clock
- Patent number 7,245,682
- Issue date Jul 17, 2007
- Intel Corporation
- Jen-Tai Hsu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for power efficient and scalable memory interface
- Patent number 7,243,176
- Issue date Jul 10, 2007
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slave I/O driver calibration using error-nulling master reference
- Patent number 7,194,559
- Issue date Mar 20, 2007
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing timing for a multi-drop bus
- Patent number 7,117,401
- Issue date Oct 3, 2006
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-ended memory interface system
- Patent number 7,010,637
- Issue date Mar 7, 2006
- Intel Corporation
- Hing Y To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing timing for a multi-drop bus
- Patent number 6,973,603
- Issue date Dec 6, 2005
- Intel Corporation
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis of a synchronization clock
- Patent number 6,941,484
- Issue date Sep 6, 2005
- Intel Corporation
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
- Patent number 6,885,959
- Issue date Apr 26, 2005
- Intel Corporation
- Joseph H. Salmon
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems having modules with on die terminations
- Patent number 6,771,515
- Issue date Aug 3, 2004
- Intel Corporation
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential memory interface system
- Patent number 6,747,483
- Issue date Jun 8, 2004
- Intel Corporation
- Hing Y. To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and an apparatus for adjusting clock signal to sample data
- Patent number 6,725,390
- Issue date Apr 20, 2004
- Intel Corporation
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems having modules with selectable on die terminations
- Patent number 6,724,082
- Issue date Apr 20, 2004
- Intel Corporation
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems having modules with buffer chips
- Patent number 6,717,823
- Issue date Apr 6, 2004
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Termination cards and systems therefore
- Patent number 6,674,648
- Issue date Jan 6, 2004
- Intel Corporation
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems having modules sharing on module terminations
- Patent number 6,674,649
- Issue date Jan 6, 2004
- Intel Corporation
- James A. McCall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
ROUTING A COMMUNICATION BUS WITHIN MULTIPLE LAYERS OF A PRINTED CIR...
- Publication number 20230108962
- Publication date Apr 6, 2023
- Xilinx, Inc.
- Xi LONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISPARATE CLOCK DOMAIN SYNCHRONIZATION
- Publication number 20110170584
- Publication date Jul 14, 2011
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dual-path clocking architecture
- Publication number 20090322398
- Publication date Dec 31, 2009
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock synchronization scheme for deskewing operations in a data int...
- Publication number 20080244298
- Publication date Oct 2, 2008
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM
- Publication number 20080244303
- Publication date Oct 2, 2008
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE
- Publication number 20080162977
- Publication date Jul 3, 2008
- Hing To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Quad rate transmitter equalization
- Publication number 20070230515
- Publication date Oct 4, 2007
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Disparate clock domain synchronization
- Publication number 20070230509
- Publication date Oct 4, 2007
- Hing (Thomas) Yan To
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for power efficient and scalable memory interface
- Publication number 20070079034
- Publication date Apr 5, 2007
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nibble de-skew method, apparatus, and system
- Publication number 20070006011
- Publication date Jan 4, 2007
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for a configurable Vcc reference and Vss referenc...
- Publication number 20060291572
- Publication date Dec 28, 2006
- Hing Y. To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Calibrating integrating receivers for source synchronous protocol
- Publication number 20060245519
- Publication date Nov 2, 2006
- Roger K. Cheng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for power efficient and scalable memory interface
- Publication number 20060101167
- Publication date May 11, 2006
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency normalization by balancing early and late clocks
- Publication number 20060067155
- Publication date Mar 30, 2006
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing timing for a multi-drop bus
- Publication number 20050195677
- Publication date Sep 8, 2005
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of integrated circuit device I/O bus timing
- Publication number 20040153684
- Publication date Aug 5, 2004
- Jonathan H. Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit and method for calibrating dram pullup Ron to pulldown Ron
- Publication number 20040083070
- Publication date Apr 29, 2004
- Intel Corporation
- Joseph H. Salmon
- G01 - MEASURING TESTING
Information Patent Application
Determining an optimal sampling clock
- Publication number 20040062329
- Publication date Apr 1, 2004
- Jen-Tai Hsu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Slave I/O driver calibration using error-nulling master reference
- Publication number 20040044808
- Publication date Mar 4, 2004
- Intel Corporation (a Delaware corporation)
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing timing for a multi-drop bus
- Publication number 20040003331
- Publication date Jan 1, 2004
- Joseph H. Salmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential memory interface system
- Publication number 20030206046
- Publication date Nov 6, 2003
- Hing Y. To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Single-ended memory interface system
- Publication number 20030208668
- Publication date Nov 6, 2003
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for capturing data from a memory subsystem
- Publication number 20030167417
- Publication date Sep 4, 2003
- Hing Y. To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS WITH SKEW CONTROL BETWEEN CLOCK AND DATA SIGNALS
- Publication number 20030122583
- Publication date Jul 3, 2003
- James A. McCall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems having modules with selectable on die terminations
- Publication number 20030016512
- Publication date Jan 23, 2003
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Application
Systems having modules with buffer chips
- Publication number 20030016513
- Publication date Jan 23, 2003
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems having modules with on die terminations
- Publication number 20030016517
- Publication date Jan 23, 2003
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Application
Systems with modules and clocking therefore
- Publication number 20030016549
- Publication date Jan 23, 2003
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modules having paths of different impedances
- Publication number 20030015346
- Publication date Jan 23, 2003
- James A. McCall
- G11 - INFORMATION STORAGE

Hing-Yan To

Person

Patents Grantslast 30 patents

On-die virtual probes (ODVP) for integrated circuitries

Printed circuit board (PCB) modular design

Disparate clock domain synchronization

Quad rate transmitter equalization

Nibble de-skew method, apparatus, and system

Disparate clock domain synchronization

Clock synchronization scheme for deskewing operations in a data int...

Dual-path clocking architecture

Calibrating integrating receivers for source synchronous protocol

Method and apparatus for power efficient and scalable memory interface

Method and system for a configurable Vcc reference and Vss referenc...

Nibble de-skew method, apparatus, and system

Modular memory controller clocking architecture

Optimization of integrated circuit device I/O bus timing

Latency normalization by balancing early and late clocks

Determining an optimal sampling clock

Method and apparatus for power efficient and scalable memory interface

Slave I/O driver calibration using error-nulling master reference

Method and apparatus for optimizing timing for a multi-drop bus

Single-ended memory interface system

Method and apparatus for optimizing timing for a multi-drop bus

Synthesis of a synchronization clock

Circuit and method for calibrating DRAM pullup Ron to pulldown Ron

Systems having modules with on die terminations

Differential memory interface system

Method and an apparatus for adjusting clock signal to sample data

Systems having modules with selectable on die terminations

Systems having modules with buffer chips

Termination cards and systems therefore

Systems having modules sharing on module terminations

Patents Applicationslast 30 patents

ROUTING A COMMUNICATION BUS WITHIN MULTIPLE LAYERS OF A PRINTED CIR...

DISPARATE CLOCK DOMAIN SYNCHRONIZATION

Dual-path clocking architecture

Clock synchronization scheme for deskewing operations in a data int...

NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM

MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE

Quad rate transmitter equalization

Disparate clock domain synchronization

Method and apparatus for power efficient and scalable memory interface

Nibble de-skew method, apparatus, and system

Method and system for a configurable Vcc reference and Vss referenc...

Calibrating integrating receivers for source synchronous protocol

Method and apparatus for power efficient and scalable memory interface

Latency normalization by balancing early and late clocks

Method and apparatus for optimizing timing for a multi-drop bus

Optimization of integrated circuit device I/O bus timing

Circuit and method for calibrating dram pullup Ron to pulldown Ron

Determining an optimal sampling clock

Slave I/O driver calibration using error-nulling master reference

Method and apparatus for optimizing timing for a multi-drop bus

Differential memory interface system

Single-ended memory interface system

Method and apparatus for capturing data from a memory subsystem

SYSTEMS WITH SKEW CONTROL BETWEEN CLOCK AND DATA SIGNALS

Systems having modules with selectable on die terminations

Systems having modules with buffer chips

Systems having modules with on die terminations

Systems with modules and clocking therefore

Modules having paths of different impedances