Hiroaki Yamoto

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test method, test system and assist board
- Patent number 7,596,730
- Issue date Sep 29, 2009
- Advantest Corporation
- Yuya Watanabe
- G01 - MEASURING TESTING
Information Patent Grant
Manufacturing method and apparatus to avoid prototype-hold in ASIC/...
- Patent number 7,178,115
- Issue date Feb 13, 2007
- Advantest Corp.
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event based IC test system
- Patent number 7,089,135
- Issue date Aug 8, 2006
- Advantest Corp.
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Grant
Method for design validation of complex IC
- Patent number 7,089,517
- Issue date Aug 8, 2006
- Advantest Corp.
- Hiroaki Yamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of evaluating core based system-on-a-chip
- Patent number 6,944,808
- Issue date Sep 13, 2005
- Advantest Corp.
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Grant
High speed semiconductor test system using radially arranged pin cards
- Patent number 6,791,316
- Issue date Sep 14, 2004
- Advantest Corp.
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for SoC design validation
- Patent number 6,678,645
- Issue date Jan 13, 2004
- Advantest Corp.
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event based semiconductor test system
- Patent number 6,678,643
- Issue date Jan 13, 2004
- Advantest Corp.
- James Alan Turnquist
- G01 - MEASURING TESTING
Information Patent Grant
Modular architecture for memory testing on event based test system
- Patent number 6,651,204
- Issue date Nov 18, 2003
- Advantest Corp.
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Grant
Application specific event based semiconductor memory test system
- Patent number 6,631,340
- Issue date Oct 7, 2003
- Advantest Corp.
- Shigeru Sugamori
- G11 - INFORMATION STORAGE
Information Patent Grant
Event based semiconductor test system
- Patent number 6,532,561
- Issue date Mar 11, 2003
- Advantest Corp.
- James Alan Turnquist
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor integrated circuit design and evaluation system using...
- Patent number 6,370,675
- Issue date Apr 9, 2002
- Advantest Corp.
- Hidenobu Matsumura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed test pattern evaluation apparatus
- Patent number 6,249,891
- Issue date Jun 19, 2001
- Advantest Corp.
- Hidenobu Matsumura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit structure for testing microprocessors and test method thereof
- Patent number 6,249,892
- Issue date Jun 19, 2001
- Advantest Corp.
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for testing embedded memories
- Patent number 6,249,889
- Issue date Jun 19, 2001
- Advantest Corp.
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for testing embedded cores based system-on-a-chip
- Patent number 6,249,893
- Issue date Jun 19, 2001
- Advantest Corp.
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit evaluation system
- Patent number 6,061,283
- Issue date May 9, 2000
- Advantest Corp.
- Koji Takahashi
- G01 - MEASURING TESTING
Information Patent Grant
Test system emulator
- Patent number 5,951,704
- Issue date Sep 14, 1999
- Advantest Corp.
- Robert F. Sauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor test system
- Patent number 5,828,985
- Issue date Oct 27, 1998
- Advantest Corp.
- Robert F. Sauer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Test method, test system and assist board
- Publication number 20070234146
- Publication date Oct 4, 2007
- Advantest Corporation
- Yuya Watanabe
- G01 - MEASURING TESTING
Information Patent Application
High speed semiconductor test system
- Publication number 20040056677
- Publication date Mar 25, 2004
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Application
Intangible property enumerating method and system
- Publication number 20040019550
- Publication date Jan 29, 2004
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Event based IC test system
- Publication number 20030217345
- Publication date Nov 20, 2003
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Application
Manufacturing method and apparatus to avoid prototype-hold in ASIC/...
- Publication number 20030217343
- Publication date Nov 20, 2003
- Rochit Rajsuman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture and design of universal IC test system
- Publication number 20030217341
- Publication date Nov 20, 2003
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Application
Event based test system having improved semiconductor characterizat...
- Publication number 20030093737
- Publication date May 15, 2003
- Michael Purtell
- G01 - MEASURING TESTING
Information Patent Application
Application specific event based semiconductor memory test system
- Publication number 20030074153
- Publication date Apr 17, 2003
- Shigeru Sugamori
- G11 - INFORMATION STORAGE
Information Patent Application
Method of evaluating core based system-on-a-chip
- Publication number 20030056163
- Publication date Mar 20, 2003
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for design validation of complex IC without us...
- Publication number 20020173942
- Publication date Nov 21, 2002
- Rochit Rajsuman
- G01 - MEASURING TESTING
Information Patent Application
Method for design validation of complex IC
- Publication number 20020040288
- Publication date Apr 4, 2002
- Hiroaki Yamoto
- G01 - MEASURING TESTING

Hiroaki Yamoto

Person

Patents Grantslast 30 patents

Test method, test system and assist board

Manufacturing method and apparatus to avoid prototype-hold in ASIC/...

Event based IC test system

Method for design validation of complex IC

Method of evaluating core based system-on-a-chip

High speed semiconductor test system using radially arranged pin cards

Method and apparatus for SoC design validation

Event based semiconductor test system

Modular architecture for memory testing on event based test system

Application specific event based semiconductor memory test system

Event based semiconductor test system

Semiconductor integrated circuit design and evaluation system using...

High speed test pattern evaluation apparatus

Circuit structure for testing microprocessors and test method thereof

Method and structure for testing embedded memories

Method and structure for testing embedded cores based system-on-a-chip

Semiconductor integrated circuit evaluation system

Test system emulator

Semiconductor test system

Patents Applicationslast 30 patents

Test method, test system and assist board

High speed semiconductor test system

Intangible property enumerating method and system

Event based IC test system

Manufacturing method and apparatus to avoid prototype-hold in ASIC/...

Architecture and design of universal IC test system

Event based test system having improved semiconductor characterizat...

Application specific event based semiconductor memory test system

Method of evaluating core based system-on-a-chip

Method and apparatus for design validation of complex IC without us...

Method for design validation of complex IC