Hirokazu Yonezawa

Person

Hyogo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Timing verification method for semiconductor integrated circuit
- Patent number 7,308,381
- Issue date Dec 11, 2007
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for statistical LSI delay simulation
- Patent number 7,239,997
- Issue date Jul 3, 2007
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis method and apparatus
- Patent number 7,222,319
- Issue date May 22, 2007
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for setting design margin for LSI
- Patent number 7,197,728
- Issue date Mar 27, 2007
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for evaluating property of integrated circuitry
- Patent number 6,869,808
- Issue date Mar 22, 2005
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for calculating temporal deterioration margin...
- Patent number 6,795,802
- Issue date Sep 21, 2004
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G01 - MEASURING TESTING
Information Patent Grant
Hot carrier effect simulation for integrated circuits
- Patent number 6,278,964
- Issue date Aug 21, 2001
- Matsushita Electric Industrial Co., Ltd.
- Jingkun Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for extracting circuit, system and method for...
- Patent number 6,219,630
- Issue date Apr 17, 2001
- Matsushita Electronics Corporation
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of LSI timing degradation simulation
- Patent number 5,974,247
- Issue date Oct 26, 1999
- Matsushita Electronics Corporation
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor utilizing a low voltage data circuit and a high voltage c...
- Patent number 5,661,413
- Issue date Aug 26, 1997
- Matsushita Electric Industrial Co., Ltd.
- Yasuhiro Tomita
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device having combined fully associative memories
- Patent number 5,475,825
- Issue date Dec 12, 1995
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having address translator and comparator for comparin...
- Patent number 5,463,751
- Issue date Oct 31, 1995
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Timing verification method for semiconductor integrated circuit
- Publication number 20070050742
- Publication date Mar 1, 2007
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for designing semiconductor intgrated circuit and system for...
- Publication number 20060107244
- Publication date May 18, 2006
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing analysis method and apparatus
- Publication number 20050276135
- Publication date Dec 15, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit simulation method and circuit simulation apparatus
- Publication number 20050177356
- Publication date Aug 11, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for setting design margin for LSI
- Publication number 20040261044
- Publication date Dec 23, 2004
- Matsushita Electric Industrial Co. Ltd.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for statistical LSI delay simulation
- Publication number 20040167756
- Publication date Aug 26, 2004
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Hirokazu Yonezawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for evaluating property of integrated circuit and method for...
- Publication number 20030054577
- Publication date Mar 20, 2003
- Matsushita Electric Industrial Co., Ltd.
- Hirokazu Yonezawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method for calculating temporal deterioration margin...
- Publication number 20020022949
- Publication date Feb 21, 2002
- Hirokazu Yonezawa
- G01 - MEASURING TESTING

Hirokazu Yonezawa

Person

Patents Grantslast 30 patents

Timing verification method for semiconductor integrated circuit

Apparatus for statistical LSI delay simulation

Timing analysis method and apparatus

Method for setting design margin for LSI

Method for evaluating property of integrated circuitry

Apparatus and method for calculating temporal deterioration margin...

Hot carrier effect simulation for integrated circuits

Apparatus and method for extracting circuit, system and method for...

Apparatus and method of LSI timing degradation simulation

Processor utilizing a low voltage data circuit and a high voltage c...

Semiconductor device having combined fully associative memories

Memory device having address translator and comparator for comparin...

Patents Applicationslast 30 patents

Timing verification method for semiconductor integrated circuit

Method for designing semiconductor intgrated circuit and system for...

Timing analysis method and apparatus

Circuit simulation method and circuit simulation apparatus

Method for setting design margin for LSI

Apparatus and method for statistical LSI delay simulation

Method for evaluating property of integrated circuit and method for...

Apparatus and method for calculating temporal deterioration margin...