Hiroki Yabe

Person

Ofuna, JP

People

Patents Grantslast 30 patents

Information Patent Grant
IR drop compensation for sensing memory
- Patent number 12,040,010
- Issue date Jul 16, 2024
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump current regulation during voltage ramp
- Patent number 11,972,807
- Issue date Apr 30, 2024
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell sensing by charge sharing between sensing nodes
- Patent number 11,869,600
- Issue date Jan 9, 2024
- SanDisk Technologies LLC
- Jiawei Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Hetero-plane data storage structures for non-volatile memory
- Patent number 11,610,625
- Issue date Mar 21, 2023
- SanDisk Technologies LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonconsecutive mapping scheme for data path circuitry in a storage...
- Patent number 11,573,914
- Issue date Feb 7, 2023
- SanDisk Technologies LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-valued programming mechanism for non-volatile memory structures
- Patent number 11,488,669
- Issue date Nov 1, 2022
- SanDisk Technologies LLC
- Keiji Nose
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with improved negative voltage capability
- Patent number 11,405,039
- Issue date Aug 2, 2022
- SanDisk Technologies LLC
- Hiroki Yabe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Threshold voltage setting with boosting read scheme
- Patent number 11,348,649
- Issue date May 31, 2022
- SanDisk Technologies LLC
- Kiyohiko Sakakibara
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter with improved negative voltage capability
- Patent number 11,336,283
- Issue date May 17, 2022
- SanDisk Technologies LLC
- Hiroki Yabe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Loop-dependent switching between program-verify techniques
- Patent number 11,250,920
- Issue date Feb 15, 2022
- SanDisk Technologies LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Word line architecture for three dimensional NAND flash memory
- Patent number 11,177,277
- Issue date Nov 16, 2021
- SanDisk Technologies LLC
- Naoki Ookuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for configurable bit line isolation in non-vo...
- Patent number 11,158,384
- Issue date Oct 26, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense amplifier architecture providing small swing voltage sensing
- Patent number 11,087,800
- Issue date Aug 10, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense amplifier architecture for low supply voltage operations
- Patent number 11,081,167
- Issue date Aug 3, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory plane structure for ultra-low read latency applications in n...
- Patent number 11,081,192
- Issue date Aug 3, 2021
- SanDiskTechnologies LLC.
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage setting with boosting read scheme
- Patent number 11,004,518
- Issue date May 11, 2021
- SanDisk Technologies LLC
- Kiyohiko Sakakibara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential dbus scheme for low-latency random read for NAND memories
- Patent number 10,984,874
- Issue date Apr 20, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Skip coding for fractional bit-per-cell NAND memories
- Patent number 10,964,390
- Issue date Mar 30, 2021
- Western Digital Technologies, Inc.
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
State coding for fractional bits-per-cell memory
- Patent number 10,910,044
- Issue date Feb 2, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area effective erase voltage isolation in NAND memory
- Patent number 10,885,984
- Issue date Jan 5, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative kick on bit line control transistors for faster bit line s...
- Patent number 10,643,677
- Issue date May 5, 2020
- SanDisk Technologies LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS FOR INCREASING CROSS BIT LINE PITCH IN NON-VO...
- Publication number 20250048637
- Publication date Feb 6, 2025
- Western Digital Technologies, Inc.
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A BIT-LINE-BIAS VERTICAL...
- Publication number 20240363170
- Publication date Oct 31, 2024
- WESTERN DIGITAL TECHNOLOGIES, INC.,
- Naoto NORIZUKI
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-WAFER BONDING FOR NAND SCALING
- Publication number 20240250007
- Publication date Jul 25, 2024
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER ARCHITECTURE PROVIDING REDUCED PROGRAM VERIFICATION...
- Publication number 20230402111
- Publication date Dec 14, 2023
- HIROKI YABE
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE PUMP CURRENT REGULATION DURING VOLTAGE RAMP
- Publication number 20230368847
- Publication date Nov 16, 2023
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
IR DROP COMPENSATION FOR SENSING MEMORY
- Publication number 20230343385
- Publication date Oct 26, 2023
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL SENSING BY CHARGE SHARING BETWEEN SENSING NODES
- Publication number 20230290415
- Publication date Sep 14, 2023
- SANDISK TECHNOLOGIES LLC
- JIAWEI XU
- G11 - INFORMATION STORAGE
Information Patent Application
Hetero-Plane Data Storage Structures For Non-Volatile Memory
- Publication number 20220406364
- Publication date Dec 22, 2022
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
Nonconsecutive Mapping Scheme for Data Path Circuitry in a Storage...
- Publication number 20220300162
- Publication date Sep 22, 2022
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-VALUED PROGRAMMING MECHANISM FOR NON-VOLATILE MEMORY STRUCTURES
- Publication number 20220208270
- Publication date Jun 30, 2022
- SANDISK TECHNOLOGIES LLC
- Keiji Nose
- G11 - INFORMATION STORAGE
Information Patent Application
LOOP-DEPENDENT SWITCHING BETWEEN PROGRAM-VERIFY TECHNIQUES
- Publication number 20210407604
- Publication date Dec 30, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING
- Publication number 20210319833
- Publication date Oct 14, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
- Publication number 20210142858
- Publication date May 13, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY
- Publication number 20210134828
- Publication date May 6, 2021
- SANDISK TECHNOLOGIES LLC
- Naoki Ookuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY PLANE STRUCTURE FOR ULTRA-LOW READ LATENCY APPLICATIONS IN N...
- Publication number 20210134375
- Publication date May 6, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE SETTING WITH BOOSTING READ SCHEME
- Publication number 20200411113
- Publication date Dec 31, 2020
- SANDISK TECHNOLOGIES LLC
- Kiyohiko Sakakibara
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE SETTING WITH BOOSTING READ SCHEME
- Publication number 20200411114
- Publication date Dec 31, 2020
- SANDISK TECHNOLOGIES LLC
- Kiyohiko Sakakibara
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE KICK ON BIT LINE CONTROL TRANSISTORS FOR FASTER BIT LINE S...
- Publication number 20200265880
- Publication date Aug 20, 2020
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
STATE CODING FOR FRACTIONAL BITS-PER-CELL MEMORY
- Publication number 20200105340
- Publication date Apr 2, 2020
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Negative Kick on Bit Line Control Transistors for Faster Bit Line S...
- Publication number 20190392874
- Publication date Dec 26, 2019
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE

Hiroki Yabe

Person

Patents Grantslast 30 patents

IR drop compensation for sensing memory

Charge pump current regulation during voltage ramp

Memory cell sensing by charge sharing between sensing nodes

Hetero-plane data storage structures for non-volatile memory

Nonconsecutive mapping scheme for data path circuitry in a storage...

Three-valued programming mechanism for non-volatile memory structures

Level shifter with improved negative voltage capability

Threshold voltage setting with boosting read scheme

Level shifter with improved negative voltage capability

Loop-dependent switching between program-verify techniques

Word line architecture for three dimensional NAND flash memory

Apparatus and methods for configurable bit line isolation in non-vo...

Sense amplifier architecture providing small swing voltage sensing

Sense amplifier architecture for low supply voltage operations

Memory plane structure for ultra-low read latency applications in n...

Threshold voltage setting with boosting read scheme

Differential dbus scheme for low-latency random read for NAND memories

Skip coding for fractional bit-per-cell NAND memories

State coding for fractional bits-per-cell memory

Area effective erase voltage isolation in NAND memory

Negative kick on bit line control transistors for faster bit line s...

Patents Applicationslast 30 patents

APPARATUS AND METHODS FOR INCREASING CROSS BIT LINE PITCH IN NON-VO...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A BIT-LINE-BIAS VERTICAL...

MULTI-WAFER BONDING FOR NAND SCALING

SENSE AMPLIFIER ARCHITECTURE PROVIDING REDUCED PROGRAM VERIFICATION...

CHARGE PUMP CURRENT REGULATION DURING VOLTAGE RAMP

IR DROP COMPENSATION FOR SENSING MEMORY

MEMORY CELL SENSING BY CHARGE SHARING BETWEEN SENSING NODES

Hetero-Plane Data Storage Structures For Non-Volatile Memory

Nonconsecutive Mapping Scheme for Data Path Circuitry in a Storage...

THREE-VALUED PROGRAMMING MECHANISM FOR NON-VOLATILE MEMORY STRUCTURES

LOOP-DEPENDENT SWITCHING BETWEEN PROGRAM-VERIFY TECHNIQUES

APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING

DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES

WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY

MEMORY PLANE STRUCTURE FOR ULTRA-LOW READ LATENCY APPLICATIONS IN N...

THRESHOLD VOLTAGE SETTING WITH BOOSTING READ SCHEME

THRESHOLD VOLTAGE SETTING WITH BOOSTING READ SCHEME

NEGATIVE KICK ON BIT LINE CONTROL TRANSISTORS FOR FASTER BIT LINE S...

STATE CODING FOR FRACTIONAL BITS-PER-CELL MEMORY

Negative Kick on Bit Line Control Transistors for Faster Bit Line S...