Patent Application
20210319833
Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory).
Memory systems can be used to store data provided by a host device (or other client). It is important that the process for programming data into the memory system be fast so that the host device (or other client) does not have to wait very long for the memory system to finish programming.
Like-numbered elements refer to common components in the different FIG.s.
Technology is described for quarter-bit line voltage sensing. In an embodiment, a three-dimensional memory array includes memory holes associated with and coupled to corresponding bit lines. Each memory hole includes one or more memory cells. The memory holes are divided into four segments, with each segment including a subset of the total number of memory holes. The memory holes in each segment are separated from one another by an intervening memory hole from outside the segment.
In an embodiment, selected memory cells in the memory holes are read in four separate read intervals. In each read interval, bit lines associated with memory holes from one of the segments are coupled to sense amplifiers, bit lines associated with memory holes from the other three segments are coupled to GROUND, and the sense amplifiers are used to determine memory states for the selected memory cells in the memory holes in the segment. Without wanting to be bound by any particular theory, it is believed that the quarter-bit line voltage sensing technology described herein may substantially reduce the effects of parasitic capacitive coupling between adjacent memory holes.
In an embodiment, the memory holes include four segments of memory holes, and the memory holes in each segment are separated from one another by an intervening memory hole from outside the segment.
The components of memory system 100 depicted in
Controller 104 includes a host interface 110 that is connected to and in communication with host 102. In one embodiment, host interface 110 provides a PCIe interface. Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 110 is also connected to a network-on-chip (NOC) 112, which is a communication subsystem on an integrated circuit. In other embodiments, NOC 112 can be replaced by a bus.
A NOC can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. In embodiments, the wires and the links of a NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges).
Connected to and in communication with NOC 112 is processor 114, ECC engine 116, memory interface 118, and DRAM controller 120. DRAM controller 120 is used to operate and communicate with local high speed volatile memory 108 (e.g., DRAM). In other embodiments, local high speed volatile memory 108 can be SRAM or another type of volatile memory.
ECC engine 116 performs error correction services. For example, ECC engine 116 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 116 is an electrical circuit programmed by software. For example, ECC engine 116 can be a processor that can be programmed. In other embodiments, ECC engine 116 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 116 is implemented by processor 114.
Processor 114 performs the various controller memory operations, such as programming, erasing, reading, as well as memory management processes. In an embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a custom and dedicated hardware circuit without any software. In an embodiment, processor 114 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit.
In many systems, non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To enable this system, the controller (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies.
One example implementation is to maintain tables (e.g., the L2P tables mentioned above) that identify a translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that local memory 108 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die 106 and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory 108.
In an embodiment, memory interface 118 communicates with one or more memory die 106. In an embodiment, memory interface 118 provides a Toggle Mode interface. Other interfaces also can be used. In some example implementations, memory interface 118 (or another portion of controller 104) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.
In an embodiment, read/write circuits 206 include multiple sense blocks 212 including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page (or multiple pages) of data in multiple memory cells to be read or programmed (written) in parallel. In an embodiment, each sense block 212 include a sense amplifier and a set of latches connected to the bit line. The latches store data to be written and/or data that has been read. In an embodiment, each sense amplifier 212 includes bit line drivers. In an embodiment, commands and data are transferred between controller 104 (
In an embodiment, control circuitry 204 cooperates with read/write circuits 206 to perform memory operations (e.g., write, read, erase, and others) on memory structure 202. In an embodiment, control circuitry 204 includes a state machine 216, an on-chip address decoder 218, and a power control circuit 220. In an embodiment, state machine 216 provides die-level control of memory operations. In an embodiment, state machine 216 is programmable by software. In other embodiments, state machine 216 does not use software and is completely implemented in hardware (e.g., electrical circuits). In some embodiments, state machine 216 can be replaced by a microcontroller or microprocessor. In an embodiment, control circuitry 204 includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.
On-chip address decoder 218 provides an address interface between addresses used by controller 104 (
For purposes of this document, control circuitry 204, read/write circuits 206, row decoder 208 and column decoder 210 comprise a control circuit for memory structure 202. In other embodiments, other circuits that support and operate on memory structure 202 can be referred to as a control circuit. For example, in some embodiments, controller 104 (
For purposes of this document, control circuitry 204, read/write circuits 206, row decoder 208 and column decoder 210 comprise peripheral circuits for memory structure 202, as they are not part of memory structure 202 but are on the same die as memory structure 202 and are used to operate memory structure 202.
In an embodiment, memory structure 202 is a three dimensional memory array of non-volatile memory cells. In an embodiment, memory structure 202 is a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may be any type of non-volatile memory that is formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells of memory structure 202 include vertical NAND strings with charge-trapping material such as described. A NAND string includes memory cells connected by a channel.
In another embodiment, memory structure 202 includes a two dimensional memory array of non-volatile memory cells. In an example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) also can be used.
The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory cell technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein.
Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories, magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable technologies for architectures of memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.
One example of a ReRAM, or PCMRAM, cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.
Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.
Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light.
A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.
The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-300 alternating dielectric layers and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers and 110 dielectric layers. More or less than 108-300 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four “fingers” by local interconnects LI.
Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in
In an embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize memory structure 202 to enable the signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells as the memory cells of a block share a common set of word lines. Although
For example,
Portion 402 depicted in
In an embodiment, the word line fingers on a common level of a block connect together to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line only connects to one memory hole in each of regions 446, 448, 450 and 452. In that implementation, each block has sixteen rows of active columns and each bit line connects to four rows in each block.
In an embodiment, all of four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together). Therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).
Although
Memory holes 410 and 454 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers and word line layers. In one embodiment, each memory hole includes a vertical NAND string. For example, memory hole 410 includes NAND string 418. Below the memory holes and the layers listed below is substrate 456, an insulating film 458 on the substrate, and source line SL. The NAND string of memory hole 410 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with
For ease of reference, drain side select layers SGD0, SGD1, SGD2 and SGD3, source side select layers SGS0, SGS1, SGS2 and SGS3, dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU, and word line layers WLL0-WLL127 collectively are referred to as the conductive layers. In an embodiment, the conductive layers are made from a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as tungsten or metal silicide. In some embodiments, different conductive layers can be formed from different materials.
Between conductive layers are dielectric layers DL0-DL143. For example, dielectric layers DL136 is above word line layer WLL126 and below word line layer WLL127. In an embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.
The non-volatile memory cells are formed along memory holes which extend through alternating conductive and dielectric layers in the stack. In an embodiment, the memory cells are arranged in NAND strings. The word line layers WLL0-WLL127 connect to memory cells (also called data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL and WLDU connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data.
In some embodiments, data memory cells and dummy memory cells may have a same structure. A dummy word line is connected to dummy memory cells. Drain side select layers SGD0, SGD1, SGD2 and SGD3 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, SGS2 and SGS3 are used to electrically connect and disconnect NAND strings from the source line SL.
In
For example, word line layer WLL127 and a portion of memory hole 410 comprise a memory cell MC1. Word line layer WLL126 and a portion of memory hole 410 comprise a memory cell MC2. Word line layer WLL125 and a portion of memory hole 410 comprise a memory cell MC3. Word line layer WLL124 and a portion of memory hole 410 comprise a memory cell MC4. Word line layer WLL123 and a portion of memory hole 410 comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.
In an embodiment, when a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 486 which is associated with the memory cell. These electrons are drawn into the charge trapping layer 486 from the channel 482, through the tunneling dielectric 484, in response to an appropriate voltage on word line region 488. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge.
In an embodiment, programming a memory cell is achieved through Fowler-Nordheim tunneling of the electrons into charge trapping layer 486. During an erase operation, the electrons return to channel 482 or holes are injected into charge trapping layer 486 to recombine with electrons. In an embodiment, erasing is achieved using hole injection into charge trapping layer 486 via a physical mechanism such as gate induced drain leakage (GIDL).
During any given memory operation, a subset of the memory cells will be identified to be subjected to one or more parts of the memory operation. These memory cells identified to be subjected to the memory operation are referred to as selected memory cells. Memory cells that have not been identified to be subjected to the memory operation are referred to as unselected memory cells. Depending on the memory architecture, the memory type, and the memory operation, unselected memory cells may be actively or passively excluded from being subjected to the memory operation.
During a memory operation some word lines are referred to as selected word lines because they are connected to selected memory cells. Unselected word lines are not connected to selected memory cells. Similarly, selected bit lines are connected to selected memory cells and unselected bit lines are not connected to selected memory cells.
Although the example memory system of
The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
In an embodiment, known as full sequence programming, memory cells can be programmed from the erased data state S0 directly to any of the programmed data states S1-S7. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program memory cells directly into data states S1, S2, S3, S4, S5, S6, and/or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and/or from data state S0 to data state S3, and so on. The arrows of
Typically, the program voltage applied to the control gates (via a selected word line) during a program operation is applied as a series of program pulses. Between programming pulses are a set of verify pulses to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 702 of
In an embodiment, the group of memory cells in a same block that are selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming.
For example, when data are written to a set of memory cells, some of the memory cells will need to store data associated with state S0, and thus such memory cells will not be programmed. Additionally, as memory cells reach their intended target data state, such memory cells will be inhibited from further programming. Those NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming.
To assist in the boosting, in step 704 the memory system will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In some embodiments, only the drain side of the channel is pre-charged. By “drain side” it is meant the portion of the NAND string on the same side of the selected word line as the bit line connection.
In step 706, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes known in the art.
In step 708, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell should be programmed, then the corresponding bit line is grounded. On the other hand, if the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to inhibit programming.
In step 708, the program pulse is applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently. That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they have been locked out from programming.
In step 710, the appropriate memory cells are verified using the appropriate set of verify reference voltages to perform one or more verify operations. In an embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage.
In step 712, it is determined whether all the memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 714. If, in step 712, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 716.
In step 716, the memory system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far failed the verify process. This counting can be done by state machine 216 (
In step 718, it is determined whether the count from step 716 is less than or equal to a predetermined limit. In an embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, than the programming process can stop and a status of “PASS” is reported in step 714. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process.
In some embodiments, the predetermined limit used in step 718 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allows for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), then the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.
If number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 720 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 20 and 30, although other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 722.
If the program counter PC is less than the program limit value PL, then the process continues at step 724 in which the Program Counter PC is incremented by 1 and the program voltage Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size (e.g., a step size of 0.1-0.4 volts). After step 724, the process loops back to step 704 and another program pulse is applied to the selected word line so that another iteration (steps 704-724) of programming process 700 is performed.
In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., read compare levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of
In an embodiment, after an appropriate read or verify voltage is applied to a selected word line, a conduction current of the memory cell is measured to determine whether the memory cell turned ON (conducts current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned ON and the voltage applied to the word line is greater than the threshold voltage of the memory cell.
If the conduction current is measured to be not greater than the certain value, then the memory cell did not turn ON, and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).
There are many ways to measure the conduction state (conductive or non-conductive) of a memory cell during a read or verify operation. In a current sensing technique, the bit line coupled to the selected memory cell is coupled to a pre-charged capacitor in a current sensing module. If the selected memory cell is in a conductive state, the pre-charged capacitor discharges through the bit line and the NAND string into the source line. In contrast, if the selected memory cell is in a non-conductive state, the pre-charged capacitor does not appreciably discharge.
After a predetermined time period, the capacitor voltage is compared to one or more predetermined reference voltages to determine the conductive state of the selected memory cell. For example, for a memory cell that stores one bit of data, if the capacitor voltage is greater than a predetermined reference voltage, the memory cell is deemed to be non-conducting (e.g., OFF). Alternatively, if the capacitor voltage is less than the predetermined reference voltage, the memory cell is deemed to be conducting (e.g., ON).
Voltage sensing, in contrast, does not involve sensing a voltage drop which is tied to a fixed current. Instead, voltage sensing involves determining whether charge sharing occurs between a capacitor in a voltage sensing module (the “sensing capacitor”) and a capacitance of the bit line. In an example embodiment, charge sharing occurs when the selected memory cell is conductive (e.g., ON), in which case the voltage of the sensing capacitor drops significantly. In contrast, little or no charge sharing occurs when the selected memory cell is non-conductive (e.g., OFF), in which case the voltage of the sensing capacitor does not drop significantly.
For example,
As described above, in connection with
In an embodiment, each of memory holes 9020, 9021, 9022, . . . , 90215 is associated with and coupled to a corresponding one of bit lines B0, B1, B2, . . . B15. Although not shown in
In some embodiments, each bit line B0, B1, B2, . . . B15 is coupled to a corresponding sense amplifier used to sense current (for current sensing) or voltage (for voltage sensing) to determine the conductivity state of a selected memory cell in the corresponding memory hole 9020, 9021, 9022, . . . , 90215 coupled to the bit line. For example, each bit line B0, B1, B2, . . . B15 is coupled to a corresponding one of sixteen sense amplifiers.
As a result of parasitic capacitive coupling between adjacent bit lines B0, B1, B2, . . . B15, the bit line settling time tBL for such memory arrays may be unnecessarily long to meet desired memory device specifications. For example, some memory devices require read times tR of 300 nsec or less. Achieving such short read times tR may require a bit line settling time tBL be about 100 nsec or less.
One technique to reduce the effects of parasitic capacitive coupling between adjacent bit lines B0, B1, B2, . . . B15 is (and hence reduce bit line settling time tBL) is sometimes referred to as “half-bit line (HBL) shielded voltage sensing.” For example,
In an embodiment of HBL shielded voltage sensing, in a first (even) read interval, each of even bit lines B0, B2, B4, B6, B8, B10, B12 and B14 is coupled to a corresponding one of eight sense amplifiers, while odd bit lines B1, B3, B5, B7, B9, B11, B13 and B15 are coupled to GROUND (or some other predetermined voltage), and the selected memory cells in even memory holes 9020, 9022, 9024, 9026, 9028, 90210, 90212 and 90214 are read. Then, in a second (odd) read interval, each of odd bit lines B1, B3, B5, B7, B9, B11, B13 and B15 is coupled to a corresponding one of the eight sense amplifiers, while even bit lines B0, B2, B4, B6, B8, B10, B12 and B14 are coupled to GROUND (or some other predetermined voltage), and the selected memory cells in odd memory holes 9021, 9023, 9025, 9027, 9029, 90211, 90213 and 90215 are read.
Although HBL shielded voltage sensing reduces the effects of parasitic capacitive coupling between adjacent bit lines B0, B1, B2, . . . B15, the technique does not reduce the effects of parasitic capacitive coupling between adjacent selected memory holes 9020, 9021, 9022, . . . , 90215. For example,
During an even read interval, parasitic capacitance Cp02 between adjacent selected memory holes 9020 and 9022 and parasitic capacitance Cp24 between adjacent selected memory holes 9022 and 9024 may slow the bit line settling time tBL of bit lines B0, B2 and B4, even though the HBL shielded voltage sensing technique shields bit lines B0 and B2 from intermediate bit line B1, and shields bit lines B2 and B4 from intermediate bit line B2. Likewise, during an odd read interval, parasitic capacitance Cp13 between adjacent selected memory holes 9021 and 9023 and parasitic capacitance Cp35 between adjacent selected memory holes 9023 and 9025 may slow the bit line settling time tBL of bit lines B1, B3 and B5, even though the HBL shielded voltage sensing technique shields bit lines B1 and B3 from intermediate bit line B2, and shields bit lines B3 and B5 from intermediate bit line B4.
Prior to time t0, the voltage of the bit line is V0i. At time t0, the bit line coupled to the selected memory cell is coupled to the sensing capacitor. If the selected memory cell is non-conductive (e.g., OFF), and the adjacent memory cell is OFF, the voltage of the sensing capacitor does not drop significantly, and at sense time t1 the voltage of the sensing capacitor remains at about V0i. However, if the selected memory cell is non-conductive (e.g., OFF), and the adjacent memory cell is ON, as a result of parasitic capacitance Cp02 between adjacent memory holes 9020 and 9022, the voltage of the sensing capacitor drops with time. For example, at sense time t1, the voltage of the sense capacitor is V0p.
If the selected memory cell is conductive (e.g., ON), and the adjacent memory cell is OFF, the voltage of the sensing capacitor drops with time. For example, at sense time t1, the voltage of the sense capacitor is V1i. However, if the selected memory cell is conductive (e.g., ON), and the adjacent memory cell is ON, the voltage of the sensing capacitor drops even more with time. For example, at sense time t1, the voltage of the sense capacitor is V1p.
In this example, the “worst case” voltage difference at sense time t1 is equal to ΔVp=V0p−V1i, which provides less margin for distinguishing between OFF and ON memory states than in the example of
Technology is described for quarter-bit line (QBL) voltage sensing.” In an embodiment, an apparatus is provided that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. In an embodiment, the memory holes include four segments of memory holes, and the memory holes in each segment are separated from one another by an intervening memory hole from outside the segment. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals. In an embodiment, the memory holes include four segments of memory holes, and the memory holes in each segment are separated from one another by an intervening memory hole from outside the segment. Without wanting to be bound by any particular theory, it is believed that the QBL voltage sensing technology described herein may substantially reduce the effects of parasitic capacitive coupling between adjacent selected memory holes.
Similarly, memory holes 9020, 9025, 9028 and 90213 are classified herein as “first quarter memory holes,” memory holes 9021, 9024, 9029 and 90212 are classified herein as “second quarter memory holes,” memory holes 9022, 9027, 90210 and 90215 are classified herein as “third quarter memory holes,” and memory holes 9023, 9026, 90211 and 90214 are classified herein as “fourth quarter memory holes.”
In step 1102, in a first read interval, each of first quarter bit lines B0, B5, B8 and B13 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1104, second quarter bit lines B1, B4, B9 and B12, third quarter bit lines B2, B7, B10 and B15, and fourth quarter bit lines B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1106, the selected memory cells of first quarter memory holes 9020, 9025, 9028 and 90213 are read.
In step 1108, in a second read interval, each of second quarter bit lines B1, B4, B9 and B12, is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1110, first quarter bit lines B0, B5, B8 and B13, third quarter bit lines B2, B7, B10 and B15, and fourth quarter bit lines and B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1112, the selected memory cells of second quarter memory holes 9021, 9024, 9029 and 90212 are read.
In step 1114, in a third read interval, each of third quarter bit lines B2, B7, B10 and B15 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1116, first quarter bit lines B0, B5, B8 and B13, second quarter bit lines B1, B4, B9 and B12, and fourth quarter bit lines B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1118, the selected memory cells of third quarter memory holes 9022, 9027, 90210 and 90215 are read.
In step 1120, in a fourth read interval, each of fourth quarter bit lines B3, B6, B11 and B14 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1122, first quarter bit lines B0, B5, B8 and B13, second quarter bit lines B1, B4, B9 and B12, and third quarter bit lines B2, B7, B10 and B15 are coupled to GROUND (or some other predetermined voltage). In step 1124, the selected memory cells of fourth quarter memory holes 9023, 9026, 90211 and 90214 are then read.
Note that example process described above and illustrated in
Referring again to
In addition, each of second quarter memory holes 9021, 9024, 9029 and 90212 are separated from one another by at least one intervening memory hole not included in the segment of second quarter memory holes 9021, 9024, 9029 and 90212. In particular, second quarter memory holes 9021 and 9024 are separated by third quarter memory hole 9022, second quarter memory holes 9021 and 9029 are separated by first quarter memory hole 9025, second quarter memory holes 9024 and 9029 are separated by fourth quarter memory hole 9026, second quarter memory holes 9024 and 90212 are separated by first quarter memory hole 9028, and second quarter memory holes 9029 and 90212 are separated by third quarter memory hole 90210. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between second quarter memory holes 9021, 9024, 9029 and 90212 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Further, each of third quarter memory holes 9022, 9027, 90210 and 90215 are separated from one another by at least one intervening memory hole not included in the segment of third quarter memory holes 9022, 9027, 90210 and 90215. In particular, third quarter memory holes 9022 and 9027 are separated by first quarter memory hole 9025, third quarter memory holes 9022 and 90210 are separated by fourth quarter memory hole 9026, third quarter memory holes 9027 and 90210 are separated by second quarter memory hole 9029, third quarter memory holes 9027 and 90215 are separated by fourth quarter memory hole 90211, and third quarter memory holes 90210 and 90215 are separated by first quarter memory hole 90213. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between third quarter memory holes 9022, 9027, 90210 and 90215 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Moreover, each of fourth quarter memory holes 9023, 9026, 90211 and 90214 are separated from one another by at least one intervening memory hole not included in the segment of fourth quarter memory holes 9023, 9026, 90211 and 90214. In particular, fourth quarter memory holes 9023 and 9026 are separated by first quarter memory hole 9025, fourth quarter memory holes 9023 and 90211 are separated by third quarter memory hole 9027, fourth quarter memory holes 9026 and 90211 are separated by second quarter memory hole 9029, fourth quarter memory holes 9026 and 90214 are separated by third quarter memory hole 90210, and fourth quarter memory holes 90211 and 90214 are separated by first quarter memory hole 90213. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between fourth quarter memory holes 9023, 9026, 90211 and 90214 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Without wanting to be bound by any particular theory, it is believed that parasitic capacitive coupling between selected memory columns in the QBL voltage sensing technique described above is much lower than that of previously known HBL shielded voltage sensing techniques such as those described above.
In an embodiment of QBL voltage sensing, selected memory cells in memory holes 9020, 9021, 9022, . . . , 90215 are read in four separate read intervals. Process 1100 of
In step 1102, in a first read interval, each of first quarter bit lines B0, B5, B8 and B13 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1104, second quarter bit lines B1, B4, B9 and B12, third quarter bit lines B2, B7, B10 and B15, and fourth quarter bit lines B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1106, the selected memory cells of first quarter memory holes 9021, 9024, 9029 and 90212 are read.
In step 1108, in a second read interval, each of second quarter bit lines B1, B4, B9 and B12, is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1110, first quarter bit lines B0, B5, B8 and B13, third quarter bit lines B2, B7, B10 and B15, and fourth quarter bit lines and B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1112, the selected memory cells of second quarter memory holes 9020, 9025, 9028 and 90213 are read.
In step 1114, in a third read interval, each of third quarter bit lines B2, B7, B10 and B15 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1116, first quarter bit lines B0, B5, B8 and B13, second quarter bit lines B1, B4, B9 and B12, and fourth quarter bit lines B3, B6, B11 and B14 are coupled to GROUND (or some other predetermined voltage). In step 1118, the selected memory cells of third quarter memory holes 9023, 9026, 90211 and 90214 are read.
In step 1120, in a fourth read interval, each of fourth quarter bit lines B3, B6, B11 and B14 is coupled to a corresponding one of four sense amplifiers (e.g., sense amplifiers SA0, SA1, SA2 and SA3, respectively). In step 1122, first quarter bit lines B0, B5, B8 and B13, second quarter bit lines B1, B4, B9 and B12, and third quarter bit lines B2, B7, B10 and B15 are coupled to GROUND (or some other predetermined voltage). In step 1124, the selected memory cells of fourth quarter memory holes 9022, 9027, 90210 and 90215 are read.
Referring again to
In addition, each of second quarter memory holes 9020, 9025, 9028 and 90213 are separated from one another by at least one intervening memory hole not included in the segment of second quarter memory holes 9020, 9025, 9028 and 90213. For example, second quarter memory holes 9020 and 9025 are separated by fourth quarter memory hole 9022, second quarter memory holes 9020 and 9028 are separated by first quarter memory hole 9024, second quarter memory holes 9025 and 9028 are separated by third quarter memory hole 9026, second quarter memory holes 9025 and 90213 are separated by first quarter memory hole 9029, and second quarter memory holes 9028 and 90213 are separated by fourth quarter memory hole 90210. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between second quarter memory holes 9020, 9025, 9028 and 90213 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Further, each of third quarter memory holes 9023, 9026, 90211 and 90214 are separated from one another by at least one intervening memory hole not included in the segment of third quarter memory holes 9023, 9026, 90211 and 90214. For example, third quarter memory holes 9023 and 9026 are separated by second quarter memory hole 9025, third quarter memory holes 9023 and 90211 are separated by fourth quarter memory hole 9027, third quarter memory holes 9026 and 90211 are separated by first quarter memory hole 9029, third quarter memory holes 9026 and 90214 are separated by fourth quarter memory hole 90210, and third quarter memory holes 90211 and 90214 are separated by second quarter memory hole 90213. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between third quarter memory holes 9023, 9026, 90211 and 90214 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Moreover, each of fourth quarter memory holes 9022, 9027, 90210 and 90215 are separated from one another by at least one intervening memory hole not included in the segment of fourth quarter memory holes 9022, 9027, 90210 and 90215. For example, fourth quarter memory holes 9022 and 9027 are separated by second quarter memory hole 9025, fourth quarter memory holes 9022 and 90210 are separated by third quarter memory hole 9026, fourth quarter memory holes 9027 and 90210 are separated by first quarter memory hole 9029, fourth quarter memory holes 9027 and 90215 are separated by third quarter memory hole 90211, and fourth quarter memory holes 90210 and 90215 are separated by second quarter memory hole 90213. Without wanting to be bound by any particular theory, it is believed that parasitic capacitance between fourth quarter memory holes 9022, 9027, 90210 and 90215 is much lower than parasitic capacitance between adjacent selected memory holes in an HBL shielded voltage sensing technique (e.g., parasitic capacitances Cp02, Cp24, Cp13 and Cp35 in
Without wanting to be bound by any particular theory, it is believed that parasitic capacitive coupling between selected memory columns in the QBL voltage sensing technique described above is much lower than that of previously known HBL shielded voltage sensing techniques such as those described above.
For example, considering only parasitic capacitance to nearest neighboring adjacent memory holes, outer memory hole 9024 has a first parasitic capacitance ca to memory hole 9020, a second parasitic capacitance cb to memory hole 9022, a third parasitic capacitance cc to memory hole 9026, and a fourth parasitic capacitance cd to memory hole 9028. In contrast, inner memory hole 9029 has a first parasitic capacitance ce to memory hole 9025, a second parasitic capacitance cf to memory hole 9026, a third parasitic capacitance cg to memory hole 9027, a fourth parasitic capacitance ch to memory hole 90210, a fifth parasitic capacitance ci to memory hole 90211, and a sixth parasitic capacitance cj to memory hole 90213. If all parasitic capacitance values are approximately the same (i.e., ca≈cb≈cc≈cd≈ce≈cf≈cg≈ch≈ci≈cj), the capacitance of each of inner memory holes 9021, 9022, 9025, 9026, 9029, 90210, 90213 and 90214 is approximately fifty percent greater than that of each of outer memory holes 9020, 9023, 9024, 9027, 9028, 90211, 90212 and 90215.
Because inner memory holes have greater parasitic capacitance than outer memory holes, bit lines coupled to inner memory holes can become a bottleneck to achieving fast bit line settling time tBL. One technique to alleviate this problem is sometimes referred to as “outer/inner bit line averaging,” in which multiple groups (e.g., group 900c of
As depicted in
One embodiment includes an apparatus that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals.
One embodiment includes a method including reading a plurality of non-volatile memory cells each disposed in a corresponding one of a plurality of memory holes, each memory hole associated with and coupled to a corresponding one of a plurality of bit lines, by in a first read interval, coupling a first segment of the bit lines to a corresponding one of a plurality of sense amplifiers, in a second read interval, coupling a second segment of the bit lines to a corresponding one of the plurality of sense amplifiers, in a third read interval, coupling a third segment of the lines to a corresponding one of the plurality of sense amplifiers, and in a fourth read interval, coupling a fourth segment of the bit lines to a corresponding one of the plurality of sense amplifiers.
One embodiment includes an apparatus that includes a first group of first memory holes and first bit lines, a second group of second memory holes and second bit lines, and a third group of third memory holes and third bit lines. Each first memory hole is associated with and coupled to a corresponding one of the first bit lines. The first memory holes include four segments of first memory holes, and the first memory holes in each segment are separated from one another by an intervening first memory hole from outside the segment. Each second memory hole is associated with and coupled to a corresponding one of the second bit lines. The second memory holes include four segments of second memory holes, and the second memory holes in each segment are separated from one another by an intervening second memory hole from outside the segment. Each third memory hole is associated with and coupled to a corresponding one of the third bit lines. The third memory holes include four segments of third memory holes. The third memory holes in each segment are separated from one another by an intervening third memory hole from outside the segment. The second group of second bit lines is disposed adjacent to and coupled to the first group of first bit lines. The third group of third bit lines is disposed adjacent to and coupled to the second group of second bit lines, the second group of second bit lines is shifted by two bit lines relative to the first group of first bit lines. The third group of third bit lines is shifted by six bit lines relative to the second group of second bit lines.
For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.
For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.
For purposes of this document, the term “based on” may be read as “based at least in part on.”
For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.
For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
