Hiromi Niiyama

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Process for fabricating a metal wiring and metal contact in a semic...
- Patent number 6,794,286
- Issue date Sep 21, 2004
- Kabushiki Kaisha Toshiba
- Hisako Aoyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device using a polymer film...
- Patent number 6,465,290
- Issue date Oct 15, 2002
- Kabushiki Kaisha Toshiba
- Kyoichi Suguro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern-forming method and lithographic system
- Patent number 6,093,931
- Issue date Jul 25, 2000
- Kabushiki Kaisha Toshiba
- Kazuyoshi Sugihara
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method of making a semiconductor device
- Patent number 6,090,699
- Issue date Jul 18, 2000
- Kabushiki Kaisha Toshiba
- Hisako Aoyama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern forming method through combined electron beam and light exp...
- Patent number 6,020,107
- Issue date Feb 1, 2000
- Kabushiki Kaisha Toshiba
- Hiromi Niiyama
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Pattern-forming method and lithographic system
- Patent number 5,994,030
- Issue date Nov 30, 1999
- Kabushiki Kaisha Toshiba
- Kazuyoshi Sugihara
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Semiconductor device having a wiring layer with a barrier layer
- Patent number 5,592,024
- Issue date Jan 7, 1997
- Kabushiki Kaisha Toshiba
- Hisako Aoyama
- H01 - BASIC ELECTRIC ELEMENTS

Hiromi Niiyama

Person

Patents Grantslast 30 patents

Process for fabricating a metal wiring and metal contact in a semic...

Method of manufacturing a semiconductor device using a polymer film...

Pattern-forming method and lithographic system

Method of making a semiconductor device

Pattern forming method through combined electron beam and light exp...

Pattern-forming method and lithographic system

Semiconductor device having a wiring layer with a barrier layer