Hirotugu Eguchi

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Tokyo, JP

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Patents Grantslast 30 patents

Information Patent Grant
Substrate bias through polysilicon line
- Patent number 4,799,101
- Issue date Jan 17, 1989
- Nippon Electric Co., Ltd.
- Hirotugu Eguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed-low power consuming IGFET integrated circuit
- Patent number 4,635,088
- Issue date Jan 6, 1987
- Nippon Electric Co., Ltd.
- Hirotugu Eguchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit
- Patent number 4,524,377
- Issue date Jun 18, 1985
- NEC Corporation
- Hirotugu Eguchi
- G11 - INFORMATION STORAGE