Hiroyuki Fujimoto

Person

Kawasaki, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device including abnormality detection circuit and se...
- Patent number 11,908,534
- Issue date Feb 20, 2024
- Fujitsu Limited
- Masahiro Yanagida
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit, test circuit, and method of testing
- Patent number 8,819,509
- Issue date Aug 26, 2014
- Fujitsu Limited
- Masahiro Yanagida
- G11 - INFORMATION STORAGE
Information Patent Grant
Evaluation board and failure location detection method
- Patent number 7,924,022
- Issue date Apr 12, 2011
- Fujitsu Limited
- Hiroyuki Fujimoto
- G01 - MEASURING TESTING
Information Patent Grant
Self-test circuit and memory device incorporating it
- Patent number 6,907,555
- Issue date Jun 14, 2005
- Fujitsu Limited
- Yukihiro Nomura
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable semiconductor memory device
- Patent number 6,262,924
- Issue date Jul 17, 2001
- Fujitsu Limited
- Yutaka Fukutani
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable semiconductor memory device
- Patent number 6,026,052
- Issue date Feb 15, 2000
- Fujitsu Limited
- Yutaka Fukutani
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable semiconductor memory device
- Patent number 5,831,933
- Issue date Nov 3, 1998
- Fujitsu Limited
- Yutaka Fukutani
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device with copy-preventive function
- Patent number 5,781,627
- Issue date Jul 14, 1998
- Fujitsu Limited
- Nobuo Ikuta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable semiconductor memory device
- Patent number 5,661,694
- Issue date Aug 26, 1997
- Fujitsu Limited
- Yutaka Fukutani
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING ABNORMALITY DETECTION CIRCUIT AND SE...
- Publication number 20220336034
- Publication date Oct 20, 2022
- Fujitsu Limited
- Masahiro Yanagida
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTO...
- Publication number 20130163356
- Publication date Jun 27, 2013
- Fujitsu Limited
- Masahiro Yanagida
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT, TEST CIRCUIT, AND METHOD OF TESTING
- Publication number 20130111281
- Publication date May 2, 2013
- Fujitsu Limited
- Masahiro Yanagida
- G11 - INFORMATION STORAGE
Information Patent Application
EVALUATION BOARD AND FAILURE LOCATION DETECTION METHOD
- Publication number 20080231287
- Publication date Sep 25, 2008
- Fujitsu Limited
- Hiroyuki FUJIMOTO
- G01 - MEASURING TESTING

Hiroyuki Fujimoto

Person

Patents Grantslast 30 patents

Semiconductor device including abnormality detection circuit and se...

Integrated circuit, test circuit, and method of testing

Evaluation board and failure location detection method

Self-test circuit and memory device incorporating it

Programmable semiconductor memory device

Programmable semiconductor memory device

Programmable semiconductor memory device

Semiconductor integrated circuit device with copy-preventive function

Programmable semiconductor memory device

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE INCLUDING ABNORMALITY DETECTION CIRCUIT AND SE...

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTO...

INTEGRATED CIRCUIT, TEST CIRCUIT, AND METHOD OF TESTING

EVALUATION BOARD AND FAILURE LOCATION DETECTION METHOD