Claims
- 1. A semiconductor memory device comprising:
- an address buffer receiving a predetermined address signal;
- first through nth address storage circuits successively storing the predetermined address signal successively output from said address buffer;
- first through nth memory regions from which data are read by decoding the predetermined address signal output from said first through nth address storage circuits, said first through nth memory regions being provided in correspondence with said first through nth address storage circuits; and
- an output switching circuit successively switching and outputting the data read from said first through nth memory regions.
- 2. The semiconductor memory device as claimed in claim 1, wherein a storage control of said first through nth address storage circuits and an output switching control of said output switching circuit are controlled based on an address signal which is different from said predetermined address signal.
- 3. A semiconductor memory device comprising:
- an address counter outputting an address signal indicating an address value by successively incrementing or decrementing from an initial value which is an address value indicated by a predetermined address signal;
- first through nth address storage circuits successively storing and outputting the address signal output from said address counter;
- first through nth memory regions from which data are read by decoding the address signal output from said first through nth address storage circuits, said first through nth memory regions being provided in correspondence with said first through nth address storage circuits; and
- an output switching circuit successively switching and outputting the data read from said first through nth memory regions.
- 4. The semiconductor memory device as claimed in claim 3, wherein a storage control of said first through nth address storage circuits and an output switching control of said output switching circuit are controlled based on an address signal which is different from said predetermined address signal.
Priority Claims (4)
Number |
Date |
Country |
Kind |
5-113458 |
May 1993 |
JPX |
|
5-312303 |
Dec 1993 |
JPX |
|
6-021479 |
Feb 1994 |
JPX |
|
6-021480 |
Feb 1994 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/237,303, filed May 3, 1994, now allowed, U.S. Pat. No. 5,661,694.
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|
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Sambandan et al. |
Sep 1993 |
|
5661694 |
Fukutani et al. |
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Divisions (1)
|
Number |
Date |
Country |
Parent |
237303 |
May 1994 |
|