Hiroyuki Yano

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Two-step chemical mechanical polish surface planarization technique
- Patent number 6,069,081
- Issue date May 30, 2000
- International Buiness Machines Corporation
- Kathryn Helen Kelleher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing apparatus and method for planarizing layer on a semicondu...
- Patent number 5,948,205
- Issue date Sep 7, 1999
- Kabushiki Kaisha Toshiba
- Masako Kodera
- B24 - GRINDING POLISHING
Information Patent Grant
Polishing apparatus and method for planarizing layer on a semicondu...
- Patent number 5,914,275
- Issue date Jun 22, 1999
- Kabushiki Kaisha Toshiba
- Masako Kodera
- B24 - GRINDING POLISHING
Information Patent Grant
Polishing method and polishing apparatus
- Patent number 5,775,980
- Issue date Jul 7, 1998
- Kabushiki Kaisha Toshiba
- Yasutaka Sasaki
- B24 - GRINDING POLISHING
Information Patent Grant
Method of forming a wiring layer for a semiconductor device
- Patent number 5,633,207
- Issue date May 27, 1997
- Kabushiki Kaisha Toshiba
- Hiroyuki Yano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing method and polishing apparatus
- Patent number 5,607,718
- Issue date Mar 4, 1997
- Kabushiki Kaisha Toshiba
- Yasutaka Sasaki
- B24 - GRINDING POLISHING
Information Patent Grant
Semiconductor planarizing apparatus
- Patent number 5,597,341
- Issue date Jan 28, 1997
- Kabushiki Kaisha Toshiba
- Masako Kodera
- B24 - GRINDING POLISHING
Information Patent Grant
Apparatus for processing semiconductor wafers
- Patent number 5,593,537
- Issue date Jan 14, 1997
- Kabushiki Kaisha Toshiba
- William J. Cote
- B24 - GRINDING POLISHING
Information Patent Grant
Method for manufacturing semiconductor device
- Patent number 5,578,531
- Issue date Nov 26, 1996
- Kabushiki Kaisha Toshiba
- Masako Kodera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for processing semiconductor wafers
- Patent number 5,534,106
- Issue date Jul 9, 1996
- Kabushiki Kaisha Toshiba
- William J. Cote
- B24 - GRINDING POLISHING
Information Patent Grant
Pad condition and polishing rate monitor using fluorescence
- Patent number 5,483,568
- Issue date Jan 9, 1996
- Kabushiki Kaisha Toshiba
- Hiroyuki Yano
- B24 - GRINDING POLISHING
Information Patent Grant
Method for planarizing a semiconductor device having a amorphous layer
- Patent number 5,445,996
- Issue date Aug 29, 1995
- Kabushiki Kaisha Toshiba
- Masako Kodera
- B24 - GRINDING POLISHING
Information Patent Grant
Method and apparatus for polishing a workpiece
- Patent number 5,398,459
- Issue date Mar 21, 1995
- Kabushiki Kaisha Toshiba
- Katsuya Okumura
- B24 - GRINDING POLISHING

Hiroyuki Yano

Person

Patents Grantslast 30 patents

Two-step chemical mechanical polish surface planarization technique

Polishing apparatus and method for planarizing layer on a semicondu...

Polishing apparatus and method for planarizing layer on a semicondu...

Polishing method and polishing apparatus

Method of forming a wiring layer for a semiconductor device

Polishing method and polishing apparatus

Semiconductor planarizing apparatus

Apparatus for processing semiconductor wafers

Method for manufacturing semiconductor device

Apparatus for processing semiconductor wafers

Pad condition and polishing rate monitor using fluorescence

Method for planarizing a semiconductor device having a amorphous layer

Method and apparatus for polishing a workpiece