Hsieh T. Hao

Person

Chappaqua, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Two-dimensional disk array
- Patent number 5,412,661
- Issue date May 2, 1995
- International Business Machines Corporation
- Hsieh T. Hao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and means for encoding and rebuilding data contents of up to...
- Patent number 5,271,012
- Issue date Dec 14, 1993
- International Business Machines Corporation
- Miguel M. Blaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction capability varied with track location on a magneti...
- Patent number 5,068,858
- Issue date Nov 26, 1991
- International Business Machines Corporation
- Miguel M. Blaum
- G11 - INFORMATION STORAGE
Information Patent Grant
(k)-Instructions-at-a-time pipelined processor for parallel executi...
- Patent number 4,594,655
- Issue date Jun 10, 1986
- International Business Machines Corporation
- Hsieh T. Hao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for implementing one machine cycle executable trap instru...
- Patent number 4,589,065
- Issue date May 13, 1986
- International Business Machines Corporation
- Marc A. Auslander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Condition register architecture for a primitive instruction set mac...
- Patent number 4,589,087
- Issue date May 13, 1986
- International Business Machines Corporation
- Marc A. Auslander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for implementing one machine cycle executable mask and ro...
- Patent number 4,569,016
- Issue date Feb 4, 1986
- International Business Machines Corporation
- Hsieh T. Hao
- G06 - COMPUTING CALCULATING COUNTING

Hsieh T. Hao

Person

Patents Grantslast 30 patents

Two-dimensional disk array

Method and means for encoding and rebuilding data contents of up to...

Error correction capability varied with track location on a magneti...

(k)-Instructions-at-a-time pipelined processor for parallel executi...

Mechanism for implementing one machine cycle executable trap instru...

Condition register architecture for a primitive instruction set mac...

Mechanism for implementing one machine cycle executable mask and ro...