Hsing-Ya Tsao

Person

Taipei, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Flash memory array having maximum and minimum threshold voltage det...
- Patent number 6,381,670
- Issue date Apr 30, 2002
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array and decoding architecture
- Patent number RE37419
- Issue date Oct 23, 2001
- Aplus Flash Technology Inc.
- Fu-Change Hsu
- 365 - Static information storage and retrieval
Information Patent Grant
Bias conditions for repair, program and erase operations of non-vol...
- Patent number 6,160,737
- Issue date Dec 12, 2000
- Aplus Flash Technology, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Positive/negative high voltage charge pump system
- Patent number 6,023,188
- Issue date Feb 8, 2000
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G05 - CONTROLLING REGULATING
Information Patent Grant
Node-precise voltage regulation for a MOS memory system
- Patent number 6,009,022
- Issue date Dec 28, 1999
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Bias condition and X-decoder circuit of flash memory array
- Patent number 5,978,277
- Issue date Nov 2, 1999
- Aplus Flash Technology, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump circuits
- Patent number 5,978,283
- Issue date Nov 2, 1999
- Aplus Flash Technology, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array and decoding architecture
- Patent number 5,953,250
- Issue date Sep 14, 1999
- Aplus Integrated Circuits, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory protection attribute status bits held in a flash memor...
- Patent number 5,930,826
- Issue date Jul 27, 1999
- Aplus Integrated Circuits, Inc.
- Peter Wung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flash memory with novel bitline decoder and sourceline latch
- Patent number 5,920,503
- Issue date Jul 6, 1999
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory with high speed erasing structure using thin oxide sem...
- Patent number 5,917,757
- Issue date Jun 29, 1999
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flash memory with high speed erasing structure using thin oxide and...
- Patent number 5,914,896
- Issue date Jun 22, 1999
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency trimmable oscillator and frequency multiplier
- Patent number 5,859,571
- Issue date Jan 12, 1999
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for preventing sub-threshold leakage in flash memory cells t...
- Patent number 5,856,945
- Issue date Jan 5, 1999
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array and decoding architecture
- Patent number 5,856,942
- Issue date Jan 5, 1999
- Aplus Integrated Circuits, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory address decoder with novel latch structure
- Patent number 5,848,000
- Issue date Dec 8, 1998
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Node-precise voltage regulation for a MOS memory system
- Patent number 5,835,420
- Issue date Nov 10, 1998
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory wordline decoder with overerase repair
- Patent number 5,822,252
- Issue date Oct 13, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory with flexible erasing size from multi-byte to multi-block
- Patent number 5,796,657
- Issue date Aug 18, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array and decoding architecture
- Patent number 5,777,924
- Issue date Jul 7, 1998
- Aplus Integrated Circuits, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory read/write controller
- Patent number 5,777,923
- Issue date Jul 7, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory with row redundancy
- Patent number 5,774,396
- Issue date Jun 30, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit-refreshable method and circuit for refreshing a nonvolatile fla...
- Patent number 5,768,193
- Issue date Jun 16, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
OR-plane memory cell array for flash memory with bit-based write ca...
- Patent number 5,748,538
- Issue date May 5, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with on-chip manufacturing and memory cell defect det...
- Patent number 5,748,545
- Issue date May 5, 1998
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flash EEPROM worldline decoder
- Patent number 5,687,121
- Issue date Nov 11, 1997
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory with divided bitline
- Patent number 5,682,350
- Issue date Oct 28, 1997
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible byte-erase flash memory and decoder
- Patent number 5,646,890
- Issue date Jul 8, 1997
- Aplus Integrated Circuits, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE

Hsing-Ya Tsao

Person

Patents Grantslast 30 patents

Flash memory array having maximum and minimum threshold voltage det...

Flash memory array and decoding architecture

Bias conditions for repair, program and erase operations of non-vol...

Positive/negative high voltage charge pump system

Node-precise voltage regulation for a MOS memory system

Bias condition and X-decoder circuit of flash memory array

Charge pump circuits

Flash memory array and decoding architecture

Flash memory protection attribute status bits held in a flash memor...

Flash memory with novel bitline decoder and sourceline latch

Flash memory with high speed erasing structure using thin oxide sem...

Flash memory with high speed erasing structure using thin oxide and...

Frequency trimmable oscillator and frequency multiplier

Method for preventing sub-threshold leakage in flash memory cells t...

Flash memory array and decoding architecture

Flash memory address decoder with novel latch structure

Node-precise voltage regulation for a MOS memory system

Flash memory wordline decoder with overerase repair

Flash memory with flexible erasing size from multi-byte to multi-block

Flash memory array and decoding architecture

Flash memory read/write controller

Flash memory with row redundancy

Bit-refreshable method and circuit for refreshing a nonvolatile fla...

OR-plane memory cell array for flash memory with bit-based write ca...

Memory device with on-chip manufacturing and memory cell defect det...

Flash EEPROM worldline decoder

Flash memory with divided bitline

Flexible byte-erase flash memory and decoder