Hugo W.-K. Chan

Person

Rancho Palos Verdes, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Planar high temperature superconductive integrated circuits for usi...
- Patent number 6,352,741
- Issue date Mar 5, 2002
- TRW Inc.
- Hugo W. K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implant-patterned superconductive device and a method for indirect...
- Patent number 6,335,108
- Issue date Jan 1, 2002
- TRW Inc.
- John R. LaGraff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using ion implantation to create normal layers in superconducting-n...
- Patent number 6,188,919
- Issue date Feb 13, 2001
- TRW Inc.
- John R. LaGraff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for indirect Ion implantation of oxide superconductive films
- Patent number 6,147,032
- Issue date Nov 14, 2000
- TRW Inc.
- John R. LaGraff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making high-T.sub.c SSNS and SNS Josephson junction
- Patent number 6,066,600
- Issue date May 23, 2000
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a low-inductance in-line resistor for superco...
- Patent number 6,051,440
- Issue date Apr 18, 2000
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar in-line resistors for superconductor circuits
- Patent number 5,912,503
- Issue date Jun 15, 1999
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-temperature SSNS and SNS Josephson junction and method of maki...
- Patent number 5,892,243
- Issue date Apr 6, 1999
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-state Josephson memory
- Patent number 5,872,731
- Issue date Feb 16, 1999
- TRW Inc.
- Hugo W-K. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Superconductive quantum interference device for digital logic circuits
- Patent number 5,863,868
- Issue date Jan 26, 1999
- TRW Inc.
- Hugo Wai-Kung Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a high performance low thermal loss bi-temperatur...
- Patent number 5,780,314
- Issue date Jul 14, 1998
- TRW Inc.
- Hugo Wai-Kung Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance, low thermal loss, bi-temperature superconductive...
- Patent number 5,773,875
- Issue date Jun 30, 1998
- TRW Inc.
- Hugo Wai-Kung Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layered superconductive interconnects
- Patent number 5,578,226
- Issue date Nov 26, 1996
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-speed gamma pulse suppression circuit for semiconductor infrar...
- Patent number 5,436,451
- Issue date Jul 25, 1995
- TRW Inc.
- Arnold H. Silver
- G01 - MEASURING TESTING
Information Patent Grant
Monolithically-integrated semiconductor/superconductor infrared det...
- Patent number 5,311,020
- Issue date May 10, 1994
- TRW Inc.
- Arnold H. Silver
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Submicron Josephson junction and method for its fabrication
- Patent number 5,286,336
- Issue date Feb 15, 1994
- TRW Inc.
- Hugo W. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Making a low resistance three layered contact for silicon devices
- Patent number 4,892,844
- Issue date Jan 9, 1990
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance metal contact for silicon devices
- Patent number 4,796,081
- Issue date Jan 3, 1989
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitride-less process for VLSI circuit device isolation
- Patent number 4,762,805
- Issue date Aug 9, 1988
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plugged poly silicon resistor load for static random access memory...
- Patent number 4,727,045
- Issue date Feb 23, 1988
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure having intermediate metal silicide layer
- Patent number 4,693,925
- Issue date Sep 15, 1987
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure having intermediate metal silicide lay...
- Patent number 4,581,815
- Issue date Apr 15, 1986
- Advanced Micro Devices, Inc.
- Robin W. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a low resistance quasi-buried contact
- Patent number 4,569,122
- Issue date Feb 11, 1986
- Advanced Micro Devices, Inc.
- Hugo W. K. Chan
- H01 - BASIC ELECTRIC ELEMENTS

Hugo W.-K. Chan

Person

Patents Grantslast 30 patents

Planar high temperature superconductive integrated circuits for usi...

Implant-patterned superconductive device and a method for indirect...

Using ion implantation to create normal layers in superconducting-n...

Method for indirect Ion implantation of oxide superconductive films

Method of making high-T.sub.c SSNS and SNS Josephson junction

Method of fabricating a low-inductance in-line resistor for superco...

Planar in-line resistors for superconductor circuits

High-temperature SSNS and SNS Josephson junction and method of maki...

Multi-state Josephson memory

Superconductive quantum interference device for digital logic circuits

Method of forming a high performance low thermal loss bi-temperatur...

High performance, low thermal loss, bi-temperature superconductive...

Multi-layered superconductive interconnects

High-speed gamma pulse suppression circuit for semiconductor infrar...

Monolithically-integrated semiconductor/superconductor infrared det...

Submicron Josephson junction and method for its fabrication

Making a low resistance three layered contact for silicon devices

Low resistance metal contact for silicon devices

Nitride-less process for VLSI circuit device isolation

Plugged poly silicon resistor load for static random access memory...

Integrated circuit structure having intermediate metal silicide layer

Integrated circuit structure having intermediate metal silicide lay...

Method of forming a low resistance quasi-buried contact