Hwong-Kwo LIN

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Write assist negative bit line voltage generator for SRAM array
- Patent number 10,672,461
- Issue date Jun 2, 2020
- NVIDIA Corporation
- Haiyan Gong
- G11 - INFORMATION STORAGE
Information Patent Grant
Mixed threshold flip-flop element to mitigate hold time penalty due...
- Patent number 10,181,842
- Issue date Jan 15, 2019
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigating external influences on long signal lines
- Patent number 9,842,631
- Issue date Dec 12, 2017
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM core cell design with write assist
- Patent number 9,542,992
- Issue date Jan 10, 2017
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Low clocking power flip-flop
- Patent number 9,525,401
- Issue date Dec 20, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell and memory
- Patent number 9,496,047
- Issue date Nov 15, 2016
- NVIDIA Corporation
- Jun Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Power savings via selection of SRAM power source
- Patent number 9,484,115
- Issue date Nov 1, 2016
- NVIDIA Corporation
- Stephen Felix
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable delay circuit and method of clock buffering
- Patent number 9,390,788
- Issue date Jul 12, 2016
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid approach to write assist for memory array
- Patent number 9,355,710
- Issue date May 31, 2016
- NVIDIA Corporation
- Haiyan Gong
- G11 - INFORMATION STORAGE
Information Patent Grant
Low tau synchronizer flip-flop with dual loop feedback approach to...
- Patent number 9,219,480
- Issue date Dec 22, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Eight transistor (8T) write assist static random access memory (SRA...
- Patent number 9,183,922
- Issue date Nov 10, 2015
- NVIDIA Corporation
- Jun Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable delay circuit and method of clock buffering
- Patent number 9,123,438
- Issue date Sep 1, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip-flop circuit having a reduced hold time requirement for a scan...
- Patent number 9,110,141
- Issue date Aug 18, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Grant
Small area low power data retention flop
- Patent number 8,988,123
- Issue date Mar 24, 2015
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual flip-flop circuit
- Patent number 8,866,528
- Issue date Oct 21, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Grant
Low power single rail input voltage level shifter
- Patent number 7,839,170
- Issue date Nov 23, 2010
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power single-rail-input voltage level shifter
- Patent number 7,830,175
- Issue date Nov 9, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-timed dynamic sense amplifier flop circuit apparatus and method
- Patent number 7,772,891
- Issue date Aug 10, 2010
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter circuit to shift signals from a logic voltage to an i...
- Patent number 7,772,885
- Issue date Aug 10, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process variation tolerant sense amplifier flop design
- Patent number 7,768,320
- Issue date Aug 3, 2010
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient high performance memory cell
- Patent number 7,649,762
- Issue date Jan 19, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sequentially-accessed 1R/1W double-pumped single port SRAM with sha...
- Patent number 7,643,330
- Issue date Jan 5, 2010
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed single-ended memory read circuit
- Patent number 7,626,871
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Active bit line charge keeper
- Patent number 7,626,878
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
2-write 3-read SRAM design using a 12-T storage cell
- Patent number 7,626,854
- Issue date Dec 1, 2009
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for preventing current leakage when a low volt...
- Patent number 7,583,126
- Issue date Sep 1, 2009
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generic flexible timer design
- Patent number 7,504,872
- Issue date Mar 17, 2009
- NVIDIA Corporation
- Hwong-Kwo Lin
- G04 - HOROLOGY
Information Patent Grant
Generic flexible timer design
- Patent number 7,492,204
- Issue date Feb 17, 2009
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power single-rail-input voltage level shifter
- Patent number 7,463,065
- Issue date Dec 9, 2008
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...
- Publication number 20170141768
- Publication date May 18, 2017
- NVIDIA Corporation
- Ge YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER SAVINGS VIA SELECTION OF SRAM POWER SOURCE
- Publication number 20160336054
- Publication date Nov 17, 2016
- NVIDIA CORPORTION
- Stephen FELIX
- G11 - INFORMATION STORAGE
Information Patent Application
LOW CLOCKING POWER FLIP-FLOP
- Publication number 20160269002
- Publication date Sep 15, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING
- Publication number 20150332757
- Publication date Nov 19, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-DIFFERENTIAL READ SCHEME FOR DUAL PORT RAM
- Publication number 20150235681
- Publication date Aug 20, 2015
- NVIDIA Corporation
- Gang Chen
- G11 - INFORMATION STORAGE
Information Patent Application
LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...
- Publication number 20150222266
- Publication date Aug 6, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY
- Publication number 20150206576
- Publication date Jul 23, 2015
- NVIDIA Corporation
- Haiyan Gong
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY
- Publication number 20150206577
- Publication date Jul 23, 2015
- NVIDIA Corporation
- Haiyan Gong
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING
- Publication number 20150103584
- Publication date Apr 16, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Application
EIGHT TRANSISTOR (8T) WRITE ASSIST STATIC RANDOM ACCESS MEMORY (SRA...
- Publication number 20140347916
- Publication date Nov 27, 2014
- NVIDIA Corporation
- Jun Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM CORE CELL DESIGN WITH WRITE ASSIST
- Publication number 20140313817
- Publication date Oct 23, 2014
- NVIDIA Corporation
- Hwong-Kwo LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES
- Publication number 20140169108
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SMALL AREA LOW POWER DATA RETENTION FLOP
- Publication number 20140167828
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL FLIP-FLOP CIRCUIT
- Publication number 20140125377
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...
- Publication number 20140129887
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
MEMORY CELL AND MEMORY
- Publication number 20140056050
- Publication date Feb 27, 2014
- Jun YANG
- G11 - INFORMATION STORAGE
Information Patent Application
GENERIC FLEXIBLE TIMER DESIGN
- Publication number 20090045847
- Publication date Feb 19, 2009
- Hwong-Kwo Lin
- G04 - HOROLOGY
Information Patent Application
APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLT...
- Publication number 20080290935
- Publication date Nov 27, 2008
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY

Hwong-Kwo LIN

Person

Patents Grantslast 30 patents

Write assist negative bit line voltage generator for SRAM array

Mixed threshold flip-flop element to mitigate hold time penalty due...

Mitigating external influences on long signal lines

SRAM core cell design with write assist

Low clocking power flip-flop

Memory cell and memory

Power savings via selection of SRAM power source

Configurable delay circuit and method of clock buffering

Hybrid approach to write assist for memory array

Low tau synchronizer flip-flop with dual loop feedback approach to...

Eight transistor (8T) write assist static random access memory (SRA...

Configurable delay circuit and method of clock buffering

Flip-flop circuit having a reduced hold time requirement for a scan...

Small area low power data retention flop

Dual flip-flop circuit

Low power single rail input voltage level shifter

Low power single-rail-input voltage level shifter

Self-timed dynamic sense amplifier flop circuit apparatus and method

Level shifter circuit to shift signals from a logic voltage to an i...

Process variation tolerant sense amplifier flop design

Area efficient high performance memory cell

Sequentially-accessed 1R/1W double-pumped single port SRAM with sha...

High-speed single-ended memory read circuit

Active bit line charge keeper

2-write 3-read SRAM design using a 12-T storage cell

Apparatus and method for preventing current leakage when a low volt...

Generic flexible timer design

Generic flexible timer design

Low power single-rail-input voltage level shifter

Patents Applicationslast 30 patents

MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...

POWER SAVINGS VIA SELECTION OF SRAM POWER SOURCE

LOW CLOCKING POWER FLIP-FLOP

CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING

PSEUDO-DIFFERENTIAL READ SCHEME FOR DUAL PORT RAM

LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...

NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY

HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY

CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING

EIGHT TRANSISTOR (8T) WRITE ASSIST STATIC RANDOM ACCESS MEMORY (SRA...

SRAM CORE CELL DESIGN WITH WRITE ASSIST

MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES

SMALL AREA LOW POWER DATA RETENTION FLOP

DUAL FLIP-FLOP CIRCUIT

FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...

MEMORY CELL AND MEMORY

GENERIC FLEXIBLE TIMER DESIGN

APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLT...