Ido Bourstein

Person

Pardes Hana, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Decoupling cells testability
- Patent number 12,345,757
- Issue date Jul 1, 2025
- Mellanox Technologies, Ltd.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Grant
Mirror image of geometrical patterns in stacked integrated circuit...
- Patent number 12,255,178
- Issue date Mar 18, 2025
- Mellanox Technologies, Ltd.
- Ido Bourstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mirror-image chips on a common substrate
- Patent number 11,705,427
- Issue date Jul 18, 2023
- Mellanox Technologies, Ltd.
- Ido Bourstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Probe card having dummy traces for testing an integrated circuit to...
- Patent number 11,422,155
- Issue date Aug 23, 2022
- MELLANOX TECHNOLOGIES, LTD.
- Konstantin Turchin
- G01 - MEASURING TESTING
Information Patent Grant
Raising maximal silicon die temperature using reliability model
- Patent number 10,915,154
- Issue date Feb 9, 2021
- MELLANOX TECHNOLOGIES TLV LTD.
- George Elias
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of wrapper cells to improve signal routing in integrated circuits
- Patent number 10,436,841
- Issue date Oct 8, 2019
- Mellanox Technologies, Ltd.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Grant
Integrating silicon photonics and laser dies using flip-chip techno...
- Patent number 10,295,740
- Issue date May 21, 2019
- Mellanox Technologies, Ltd.
- Ido Bourstein
- G02 - OPTICS
Information Patent Grant
Method and apparatus for valid encoding
- Patent number 9,621,303
- Issue date Apr 11, 2017
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sensing arrangement for sensing a voltage from multiple voltage sou...
- Patent number 9,606,150
- Issue date Mar 28, 2017
- Marvell International Ltd.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Grant
AVS master slave
- Patent number 9,465,396
- Issue date Oct 11, 2016
- Marvell Israel (M.I.S.L) Ltd.
- Michael Moshe
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit interposer and method of manufacturing the same
- Patent number 9,455,193
- Issue date Sep 27, 2016
- Marvell Israel (M.I.S.L) Ltd.
- Carol Pincu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for regulator control
- Patent number 9,436,203
- Issue date Sep 6, 2016
- Marvell World Trade Ltd.
- Reuven Ecker
- G05 - CONTROLLING REGULATING
Information Patent Grant
Switching arrangement for power supply from multiple power sources
- Patent number 9,337,660
- Issue date May 10, 2016
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for reducing jitter
- Patent number 9,124,461
- Issue date Sep 1, 2015
- Marvell Israel (M.I.S.L) Ltd.
- Liav Ben Artsi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for testing integrated circuits
- Patent number 9,086,453
- Issue date Jul 21, 2015
- MARVELL INERNATIONAL LTD.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit interposer and method of manufacturing the same
- Patent number 9,006,908
- Issue date Apr 14, 2015
- Marvell Israel (M.I.S.L) Ltd.
- Carol Pincu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
AVS-adaptive voltage scaling
- Patent number 8,972,755
- Issue date Mar 3, 2015
- Marvell Israel (M.I.S.L) Ltd.
- Meir Hasko
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for testing integrated circuits
- Patent number 8,866,501
- Issue date Oct 21, 2014
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Grant
AVS—adaptive voltage scaling
- Patent number 8,615,669
- Issue date Dec 24, 2013
- Marvell Israel (M.I.S.L) Ltd.
- Meir Hasko
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
AVS-adaptive voltage scaling
- Patent number 8,370,654
- Issue date Feb 5, 2013
- Marvell Israel (M.I.S.L) Ltd.
- Meir Hasko
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
No stress level shifter
- Patent number 8,169,234
- Issue date May 1, 2012
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Isolated level shifter
- Patent number 7,936,182
- Issue date May 3, 2011
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for generating a clock signal
- Patent number 7,932,768
- Issue date Apr 26, 2011
- Marvell Israel (M.I.S.L.) Ltd.
- Ido Bourstein
- G11 - INFORMATION STORAGE
Information Patent Grant
No stress level shifter
- Patent number 7,884,646
- Issue date Feb 8, 2011
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating differential signal
- Patent number 7,804,431
- Issue date Sep 28, 2010
- Marvell Israel (M.I.S.L) Ltd.
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally controlled oscillator and associated method
- Patent number 7,667,948
- Issue date Feb 23, 2010
- Marvell Israel (M.I.S.L) Ltd.
- Gil Asa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for generating a clock signal
- Patent number 7,652,516
- Issue date Jan 26, 2010
- Marvell Israel (M.I.S.L.) Ltd.
- Ido Bourstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating differential signal
- Patent number 7,592,934
- Issue date Sep 22, 2009
- Marvell Israel (MISL), Ltd
- Ido Bourstein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally controlled oscillator and associated method
- Patent number 7,330,081
- Issue date Feb 12, 2008
- Marvell Semiconductor Israel Ltd.
- Gil Asa
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Mirror image of geometrical patterns in stacked integrated circuit...
- Publication number 20250183231
- Publication date Jun 5, 2025
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIGITAL-DOMAIN-INTEGRATED, VOLTAGE-TO-FREQUENCY TEMPERATURE SENSOR
- Publication number 20240410762
- Publication date Dec 12, 2024
- NVIDIA Corporation
- Naor Peretz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Decoupling Cells Testability
- Publication number 20240369619
- Publication date Nov 7, 2024
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- G01 - MEASURING TESTING
Information Patent Application
Stacking of integrated circuit dies
- Publication number 20230238358
- Publication date Jul 27, 2023
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Mirror-image chips on a common substrate
- Publication number 20230105149
- Publication date Apr 6, 2023
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Raising Maximal Silicon Die Temperature Using Reliability Model
- Publication number 20210041927
- Publication date Feb 11, 2021
- Mellanox Technologies TLV Ltd.
- George Elias
- G05 - CONTROLLING REGULATING
Information Patent Application
Probe Card for Testing a Die to Be Installed in a Multichip-Module
- Publication number 20200379006
- Publication date Dec 3, 2020
- MELLANOX TECHNOLOGIES, LTD.
- Konstantin Turchin
- G01 - MEASURING TESTING
Information Patent Application
Use of wrapper cells to improve signal routing in integrated circuits
- Publication number 20190227124
- Publication date Jul 25, 2019
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrating Silicon Photonics and Laser Dies using Flip-Chip Techno...
- Publication number 20180011248
- Publication date Jan 11, 2018
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- G02 - OPTICS
Information Patent Application
METHOD AND APPARATUS FOR VALID ENCODING
- Publication number 20150212156
- Publication date Jul 30, 2015
- MARVEL ISRAEL (M.I.S.L) LTD.
- Ido BOURSTEIN
- G01 - MEASURING TESTING
Information Patent Application
Integrated Circuit Interposer and Method of Manufacturing the Same
- Publication number 20150194414
- Publication date Jul 9, 2015
- MARVELL ISRAEL (M.I.S.L) LTD.
- Carol Pincu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR REACTING TO A CHANGE IN SUPPLY VOLTAGE
- Publication number 20150180482
- Publication date Jun 25, 2015
- MARVELL ISRAEL (M.I.S.L) LTD.
- Ido BOURSTEIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR REGULATOR CONTROL
- Publication number 20140097694
- Publication date Apr 10, 2014
- Marvell World Trade Ltd.
- Reuven ECKER
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
Integrated Circuit Interposer and Method of Manufacturing the Same
- Publication number 20140035093
- Publication date Feb 6, 2014
- Marvell International Ltd.
- Carol Pincu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AVS MASTER SLAVE
- Publication number 20130293276
- Publication date Nov 7, 2013
- Michael MOSHE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING JITTER
- Publication number 20130022134
- Publication date Jan 24, 2013
- Liav BEN ARTSI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS
- Publication number 20120293195
- Publication date Nov 22, 2012
- Ido BOURSTEIN
- G01 - MEASURING TESTING
Information Patent Application
Method and Apparatus for Testing Integrated Circuits
- Publication number 20120049873
- Publication date Mar 1, 2012
- Ido BOURSTEIN
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and Method for Generating a Clock Signal
- Publication number 20100102869
- Publication date Apr 29, 2010
- Gil Stoler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR GENERATING A CLOCK SIGNAL
- Publication number 20080094117
- Publication date Apr 24, 2008
- Gil Stoler
- G06 - COMPUTING CALCULATING COUNTING

Ido Bourstein

Person

Patents Grantslast 30 patents

Decoupling cells testability

Mirror image of geometrical patterns in stacked integrated circuit...

Mirror-image chips on a common substrate

Probe card having dummy traces for testing an integrated circuit to...

Raising maximal silicon die temperature using reliability model

Use of wrapper cells to improve signal routing in integrated circuits

Integrating silicon photonics and laser dies using flip-chip techno...

Method and apparatus for valid encoding

Sensing arrangement for sensing a voltage from multiple voltage sou...

AVS master slave

Integrated circuit interposer and method of manufacturing the same

Method and apparatus for regulator control

Switching arrangement for power supply from multiple power sources

Method and apparatus for reducing jitter

Method and apparatus for testing integrated circuits

Integrated circuit interposer and method of manufacturing the same

AVS-adaptive voltage scaling

Method and apparatus for testing integrated circuits

AVS—adaptive voltage scaling

AVS-adaptive voltage scaling

No stress level shifter

Isolated level shifter

Apparatus and method for generating a clock signal

No stress level shifter

Method and apparatus for generating differential signal

Digitally controlled oscillator and associated method

Apparatus and method for generating a clock signal

Method and apparatus for generating differential signal

Digitally controlled oscillator and associated method

Patents Applicationslast 30 patents

Mirror image of geometrical patterns in stacked integrated circuit...

DIGITAL-DOMAIN-INTEGRATED, VOLTAGE-TO-FREQUENCY TEMPERATURE SENSOR

Decoupling Cells Testability

Stacking of integrated circuit dies

Mirror-image chips on a common substrate

Raising Maximal Silicon Die Temperature Using Reliability Model

Probe Card for Testing a Die to Be Installed in a Multichip-Module

Use of wrapper cells to improve signal routing in integrated circuits

Integrating Silicon Photonics and Laser Dies using Flip-Chip Techno...

METHOD AND APPARATUS FOR VALID ENCODING

Integrated Circuit Interposer and Method of Manufacturing the Same

APPARATUS AND METHOD FOR REACTING TO A CHANGE IN SUPPLY VOLTAGE

METHOD AND APPARATUS FOR REGULATOR CONTROL

Integrated Circuit Interposer and Method of Manufacturing the Same

AVS MASTER SLAVE

METHOD AND APPARATUS FOR REDUCING JITTER

METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS

Method and Apparatus for Testing Integrated Circuits

Apparatus and Method for Generating a Clock Signal

APPARATUS AND METHOD FOR GENERATING A CLOCK SIGNAL