Patent Application
20230105149
The present invention relates generally to integrated circuit (IC) chips, and particularly to multi-chip modules and methods for their manufacture.
A multi-chip module is an electronic assembly in which multiple IC dies are mounted and interconnected on a common substrate, which is then packaged as if it were a single, larger IC. The substrate may itself comprise a semiconductor chip with suitable internal and external mounting pads, along with interconnecting traces; or it may alternatively comprise a ceramic or laminated printed circuit board.
Embodiments of the present invention that are described hereinbelow provide improved multi-die IC devices and methods for the design and fabrication of such devices.
There is therefore provided, in accordance with an embodiment of the invention, an electronic device, including a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.
In some embodiments, the second IC die is mounted on the substrate in a location adjacent to the first IC die. In a disclosed embodiment, the first and second IC dies are mounted on the substrate such that respective first edges of the first and second IC dies are in mutual proximity, and the predefined set of circuit components includes an interface circuit, which is disposed in proximity to respective second edges of the first and second IC dies, opposite the respective first edges.
Additionally or alternatively, the device includes a third IC die including a switching core mounted on the substrate, wherein the first and second IC dies include switch ports and are mounted on the substrate in respective locations adjacent to the third IC die.
Further additionally or alternatively, in some embodiments in which the predefined set of circuit components includes an interface circuit, which is disposed in proximity to respective edges of the first and second IC dies, and the contact pads include at least first and second contact pads, the traces include a first trace connecting the first contact pad to the interface circuit of the first IC die and a second trace connecting the second contact pad to the interface circuit of the second IC die, wherein the second trace is routed alongside the first trace on the substrate. In a disclosed embodiment, the first and second contact pads are mutually adjacent. Additionally or alternatively, the device includes a third IC die, and the first and second IC dies are mounted on the substrate adjacent to different, respective edges of the third IC die.
There is also provided, in accordance with an embodiment of the invention, a method for fabricating an electronic device. The method includes providing a substrate having contact pads disposed thereon and traces interconnecting the contact pads. First and second integrated circuit (IC) dies are mounted on the substrate. The first IC die includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. The second IC die includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.
In some embodiments, the method includes fabricating first and second pluralities of the first and second IC dies on a single semiconductor wafer, and dicing the semiconductor wafer to provide the first and second IC dies for mounting on the substrate. In a disclosed embodiment, fabricating the first and second pluralities of the first and second IC dies includes applying a photolithographic process to the semiconductor wafer using a reticle containing both the first and second geometrical patterns.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:
Some multi-chip modules contain multiple IC dies with similar or identical functionalities. For example, a large-scale high-speed packet switch may contain one IC die comprising a switching core and multiple IC dies comprising switch ports, which are connected to the switching core through traces on the substrate. Although dividing the functions of the switch among multiple chips increases the complexity of assembling the multi-chip module, it is often economically advantageous because of the greater yield that can be achieved in producing smaller dies. In some applications, the division into several dies is unavoidable as the silicon die size is limited by the manufacturing reticle size, which is not large enough to accommodate all the required functionality and/or features.
Another consideration in designing the multi-chip module is the length and complexity of the traces on the module substrate that will be needed to connect the IC dies to one another and to the contact pads that connect the module to external interfaces. In this regard, it is desirable that the circuit components within each die be laid out in a way that simplifies the layout of the traces on the substrate and avoids the need for long traces traversing through multiple metal layers. For this reason, for example, interface and other input/output (I/O) circuits within the IC dies are advantageously placed at the edges of the dies in locations that can be accessed easily by traces on the module substrate.
When multiple IC dies with the same set of circuit components and functionalities are used in the same multi-chip module, the dies typically all have the same geometrical layout. Using identical dies is convenient, since many dies can then be fabricated together on the same semiconductor wafer, using the same photolithographic mask. When these identical IC dies are laid out in the multi-chip module, however, some of the interface circuits may be in inconvenient locations. For example, when two identical dies having an interface circuit in the lower-right corner are mounted side-by-side, the interface circuit of the right-hand die will be at the outer edge of the layout and thus can be reached easily by traces on the substrate; but the interface circuit of the left-hand die will be surrounded by other circuit components and may be harder to reach. (The terms “left,” “right,” “upper” and “lower” are used here arbitrarily for the sake of conceptual clarity and do not necessarily have any functional meaning.) It would be possible to redesign the left-hand die to avoid this problem, but such a redesign will incur high costs in terms of re-engineering, testing, and mask production.
Embodiments of the present invention that are described herein address these problems by providing pairs of mirror-image dies, which are then mounted on the same substrate. In other words, after a first die is designed and verified, with a set of circuit components arranged in a certain geometrical pattern, the second die is created with the same set of circuit components in a geometrical pattern that is a mirror image of the first die. (The mirror image is with respect to a certain axis in the plane of the dies about which the geometrical pattern is non-symmetrical.) As all the layers in the second die, as well as the reticles that are used to fabricate them, are simply mirror images of those in the first die, there is no need for substantial redesign and testing prior to producing the second die, and consequently little added cost.
Thus, in the disclosed embodiments, the second die is functionally identical to the first die, but with a mirror-image geometrical layout of circuit components and contact pads. The first and second dies can then be mixed as desired on the substrate of the multi-chip module so as to simplify and optimize the layouts of the pads and traces on the substrate. Referring back to the previous example, the IC dies can be mounted, for instance, so that the interface circuits of both the “left-hand” and “right-hand” dies are disposed in proximity to the outer edges of the dies.
In the example shown in
In the pictured embodiment, a pair of dies 26 and 28 is mounted adjacent to each side of die 24. Dies 26 and 28 in each pair are mounted to that the inner edges of the dies are in mutual proximity, while interface circuit 30 in each die 26, 28 is located at the outer edge of the die (which may be either the left or the right edge, depending on the disposition of the die). Pads 32 on substrate 22 connect interface circuits 30 via traces 36 to pads 34 for external connection. Because the interface circuits are conveniently located at the outer edges of dies 26, 28, traces 36 are short and simple to route. (By contrast, if only dies 26 were used in assembly 20, the traces connecting to the interface circuits of at least some of the dies would have to be routed underneath the dies to reach the locations of pads 34.) Specifically, in the present example, the trace 36 that connects to interface circuit 30 of each die 26 is routed alongside the trace 36 that connects to the interface circuit of the neighboring die 28 that is mounted around the corner of die 24. The contact pads 34 on substrate 22 to which these pairs of traces are connected are likewise mutually adjacent.
Although the example shown in
Reference is now made to
Reticle 40 in this example is designed for simultaneous photolithographic exposure of multiple dies, including a first die pattern 42 and a second die pattern 44. Patterns 42 and 44 are mirror-images of one another, reflected above an axis 46. The elements of patterns 42 and 44 would ordinarily correspond to parts of circuit components. After design and verification of the elements of pattern 42, for example, using electronic design automation (EDA) tools that are known in the art, these elements are flipped about axis 46 by a simple geometrical operation of the EDA tools to create pattern 44. Flipping the patterns in this manner typically has no effect on their functionality. Therefore, little or no added testing is required to verify pattern 44.
To fabricate dies 52 and 54 on wafer 50, reticle 40 is stepped across the wafer, and photoresist on the wafer surface is exposed through the reticle at each step. Thus, alternating rows of mirror-image dies 52 and 54 are exposed and etched across the wafer surface. Following these fabrication steps, wafer 50 is diced along scribe lines 56 to provide multiple dies 52 and multiple dies 54. After testing, the dies are mounted on a substrate, for example in the manner in which dies 26 and 28 are mounted on substrate 22 (
It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.
