Il-Seok Son

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,761
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,762
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for revealing a backside of an integrated circuit device...
- Patent number 11,594,452
- Issue date Feb 28, 2023
- Intel Corporation
- Il-Seok Son
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 11,264,493
- Issue date Mar 1, 2022
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for revealing a backside of an integrated circuit device...
- Patent number 10,896,847
- Issue date Jan 19, 2021
- Intel Corporation
- Il-Seok Son
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming backside self-aligned vias and structures formed...
- Patent number 10,797,139
- Issue date Oct 6, 2020
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for revealing a backside of an integrated circuit device...
- Patent number 10,490,449
- Issue date Nov 26, 2019
- Intel Corporation
- Il-Seok Son
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming backside self-aligned vias and structures formed...
- Patent number 10,367,070
- Issue date Jul 30, 2019
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Partial layer transfer system and method
- Patent number 10,236,282
- Issue date Mar 19, 2019
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming under device interconnect structures
- Patent number 9,721,898
- Issue date Aug 1, 2017
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming under device interconnect structures
- Patent number 9,490,201
- Issue date Nov 8, 2016
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20240413237
- Publication date Dec 12, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20220140127
- Publication date May 5, 2022
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20220140128
- Publication date May 5, 2022
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...
- Publication number 20210104435
- Publication date Apr 8, 2021
- Intel Corporation
- Il-Seok SON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...
- Publication number 20190371666
- Publication date Dec 5, 2019
- Intel Corporation
- Il-Seok SON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED...
- Publication number 20190326405
- Publication date Oct 24, 2019
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED...
- Publication number 20180248012
- Publication date Aug 30, 2018
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...
- Publication number 20180233409
- Publication date Aug 16, 2018
- Intel Corporation
- Il-Seok SON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20180219090
- Publication date Aug 2, 2018
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARTIAL LAYER TRANSFER SYSTEM AND METHOD
- Publication number 20160233206
- Publication date Aug 11, 2016
- Intel Corporation
- PATRICK MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES
- Publication number 20140264739
- Publication date Sep 18, 2014
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS

Il-Seok Son

Person

Patents Grantslast 30 patents

Wrap-around source/drain method of making contacts for backside metals

Wrap-around source/drain method of making contacts for backside metals

Techniques for revealing a backside of an integrated circuit device...

Wrap-around source/drain method of making contacts for backside metals

Techniques for revealing a backside of an integrated circuit device...

Methods of forming backside self-aligned vias and structures formed...

Techniques for revealing a backside of an integrated circuit device...

Methods of forming backside self-aligned vias and structures formed...

Partial layer transfer system and method

Methods of forming under device interconnect structures

Methods of forming under device interconnect structures

Patents Applicationslast 30 patents

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...

TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...

METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED...

METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED...

TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE...

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

PARTIAL LAYER TRANSFER SYSTEM AND METHOD

METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES