Ilya V. Neznanov

Person

Moscow, RU

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for processing signals carrying modulation-encoded parity...
- Patent number 9,337,866
- Issue date May 10, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Elyar Eldarovich Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel decoder for multiple wireless standards
- Patent number 9,319,181
- Issue date Apr 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable circuit for high speed computation of the interleaver...
- Patent number 8,938,654
- Issue date Jan 20, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet router having a hierarchical buffer structure
- Patent number 8,923,315
- Issue date Dec 30, 2014
- LSI Corporation
- Pavel Aleksandrovich Aliseychik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimization of data processors with irregular patterns
- Patent number 8,923,413
- Issue date Dec 30, 2014
- LSI Corporation
- Yurii S. Shutkin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
No-delay microsequencer
- Patent number 8,868,890
- Issue date Oct 21, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L-value generation in a decoder
- Patent number 8,842,784
- Issue date Sep 23, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Andrey P. Sokolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable parity encoder
- Patent number 8,775,893
- Issue date Jul 8, 2014
- LSI Corporation
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Radix-4 viterbi forward error correction decoding
- Patent number 8,775,914
- Issue date Jul 8, 2014
- LSI Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable encoding per multiple communications standards
- Patent number 8,700,969
- Issue date Apr 15, 2014
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Branch metrics calculation for multiple communications standards
- Patent number 8,699,396
- Issue date Apr 15, 2014
- LSI Corporation
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timer manager architecture based on binary heap
- Patent number 8,656,206
- Issue date Feb 18, 2014
- LSI Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable BCH decoder
- Patent number 8,621,329
- Issue date Dec 31, 2013
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel true random number generator architecture
- Patent number 8,539,009
- Issue date Sep 17, 2013
- LSI Corporation
- Pavel A. Aliseychik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for using the universal multipole for the impleme...
- Patent number 8,527,851
- Issue date Sep 3, 2013
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BCH or reed-solomon decoder with syndrome modification
- Patent number 8,397,143
- Issue date Mar 12, 2013
- LSI Corporation
- Ilya V. Neznanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Soft reed-solomon decoder based on error-and-erasure reed-solomon d...
- Patent number 8,365,054
- Issue date Jan 29, 2013
- LSI Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scheme for erasure locator polynomial calculation in error-and-eras...
- Patent number 8,286,060
- Issue date Oct 9, 2012
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reed-solomon decoder with a variable number of correctable errors
- Patent number 8,209,589
- Issue date Jun 26, 2012
- LSI Corporation
- Alexandre Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable Reed-Solomon decoder based on modified Forney syndromes
- Patent number 8,181,096
- Issue date May 15, 2012
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable redundancy reed-solomon encoder
- Patent number 8,176,397
- Issue date May 8, 2012
- LSI Corporation
- Pavel Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 8,037,432
- Issue date Oct 11, 2011
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Low area architecture in BCH decoder
- Patent number 7,823,050
- Issue date Oct 26, 2010
- LSICorporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 7,424,687
- Issue date Sep 9, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for tiling memories in integrated circuit layout
- Patent number 7,389,484
- Issue date Jun 17, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RRAM controller built in self test memory
- Patent number 7,356,743
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Andrey Nikitin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory generation and placement
- Patent number 7,155,688
- Issue date Dec 26, 2006
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS FOR PROCESSING SIGNALS CARRYING MODULATION-ENCODED PARITY...
- Publication number 20140359394
- Publication date Dec 4, 2014
- LSI Corporation
- Elyar Eldarovich Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
- Publication number 20140223267
- Publication date Aug 7, 2014
- LSI Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULATION CODING OF PARITY BITS GENERATED USING AN ERROR-CORRECTIO...
- Publication number 20140164876
- Publication date Jun 12, 2014
- Elyar Eldarovich Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED ADD-COMPARE-SELECT CIRCUIT
- Publication number 20140040342
- Publication date Feb 6, 2014
- LSI Corporation
- Andrey P. Sokolov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ROUTER HAVING A HIERARCHICAL BUFFER STRUCTURE
- Publication number 20140023085
- Publication date Jan 23, 2014
- LSI Corporation
- Pavel Aleksandrovich Aliseychik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Optimization of Data Processors with Irregular Patterns
- Publication number 20130235907
- Publication date Sep 12, 2013
- LSI Corporation
- Yurii S. Shutkin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VARIABLE PARITY ENCODER
- Publication number 20130019139
- Publication date Jan 17, 2013
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER
- Publication number 20120284731
- Publication date Nov 8, 2012
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DECODER FOR MULTIPLE WIRELESS STANDARDS
- Publication number 20120281790
- Publication date Nov 8, 2012
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP
- Publication number 20120278648
- Publication date Nov 1, 2012
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATION OF JACOBIAN LOGARITHM OPERATION
- Publication number 20120166501
- Publication date Jun 28, 2012
- Andrey P. Sokolov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
- Publication number 20120144274
- Publication date Jun 7, 2012
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS
- Publication number 20120137190
- Publication date May 31, 2012
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS
- Publication number 20120134325
- Publication date May 31, 2012
- Pavel A. Panteleev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
L-VALUE GENERATION IN A DECODER
- Publication number 20120128102
- Publication date May 24, 2012
- Andrey P. Sokolov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NO-DELAY MICROSEQUENCER
- Publication number 20120117359
- Publication date May 10, 2012
- Yurii S. Shutkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE BCH DECODER
- Publication number 20120054586
- Publication date Mar 1, 2012
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE CIRCUIT FOR HIGH SPEED COMPUTATION OF THE INTERLEAVER...
- Publication number 20110239079
- Publication date Sep 29, 2011
- Andrey P. Sokolov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION
- Publication number 20100299580
- Publication date Nov 25, 2010
- Ilya V. Neznanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON D...
- Publication number 20100281344
- Publication date Nov 4, 2010
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARALLEL TRUE RANDOM NUMBER GENERATOR ARCHITECTURE
- Publication number 20100153478
- Publication date Jun 17, 2010
- Pavel A. Aliseychik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE REDUNDANCY REED-SOLOMON ENCODER
- Publication number 20100070831
- Publication date Mar 18, 2010
- Elyar Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS
- Publication number 20100070832
- Publication date Mar 18, 2010
- Alexandre Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for using the universal multipole for the impleme...
- Publication number 20100031126
- Publication date Feb 4, 2010
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERAS...
- Publication number 20100031127
- Publication date Feb 4, 2010
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES
- Publication number 20090158118
- Publication date Jun 18, 2009
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...
- Publication number 20080295044
- Publication date Nov 27, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Area Architecture in BCH Decoder
- Publication number 20080155381
- Publication date Jun 26, 2008
- LSI Logic Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for tiling memories in integrated circuit layout
- Publication number 20070108961
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for mapping design memories to integrated circ...
- Publication number 20070113212
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING

Ilya V. Neznanov

Person

Patents Grantslast 30 patents

Apparatus for processing signals carrying modulation-encoded parity...

Parallel decoder for multiple wireless standards

Programmable circuit for high speed computation of the interleaver...

Packet router having a hierarchical buffer structure

Optimization of data processors with irregular patterns

No-delay microsequencer

L-value generation in a decoder

Variable parity encoder

Radix-4 viterbi forward error correction decoding

Reconfigurable encoding per multiple communications standards

Branch metrics calculation for multiple communications standards

Timer manager architecture based on binary heap

Reconfigurable BCH decoder

Parallel true random number generator architecture

System and method for using the universal multipole for the impleme...

BCH or reed-solomon decoder with syndrome modification

Soft reed-solomon decoder based on error-and-erasure reed-solomon d...

Scheme for erasure locator polynomial calculation in error-and-eras...

Reed-solomon decoder with a variable number of correctable errors

Configurable Reed-Solomon decoder based on modified Forney syndromes

Variable redundancy reed-solomon encoder

Method and apparatus for mapping design memories to integrated circ...

Low area architecture in BCH decoder

Method and apparatus for mapping design memories to integrated circ...

Method and apparatus for tiling memories in integrated circuit layout

RRAM controller built in self test memory

Memory generation and placement

Patents Applicationslast 30 patents

APPARATUS FOR PROCESSING SIGNALS CARRYING MODULATION-ENCODED PARITY...

RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING

MODULATION CODING OF PARITY BITS GENERATED USING AN ERROR-CORRECTIO...

HIGH SPEED ADD-COMPARE-SELECT CIRCUIT

PACKET ROUTER HAVING A HIERARCHICAL BUFFER STRUCTURE

Optimization of Data Processors with Irregular Patterns

VARIABLE PARITY ENCODER

TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER

PARALLEL DECODER FOR MULTIPLE WIRELESS STANDARDS

TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP

COMPUTATION OF JACOBIAN LOGARITHM OPERATION

RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING

RECONFIGURABLE ENCODING PER MULTIPLE COMMUNICATIONS STANDARDS

BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS

L-VALUE GENERATION IN A DECODER

NO-DELAY MICROSEQUENCER

RECONFIGURABLE BCH DECODER

PROGRAMMABLE CIRCUIT FOR HIGH SPEED COMPUTATION OF THE INTERLEAVER...

BCH OR REED-SOLOMON DECODER WITH SYNDROME MODIFICATION

SOFT REED-SOLOMON DECODER BASED ON ERROR-AND-ERASURE REED-SOLOMON D...

PARALLEL TRUE RANDOM NUMBER GENERATOR ARCHITECTURE

VARIABLE REDUNDANCY REED-SOLOMON ENCODER

REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS

System and method for using the universal multipole for the impleme...

SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERAS...

CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES

METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...

Low Area Architecture in BCH Decoder

Method and apparatus for tiling memories in integrated circuit layout

Method and apparatus for mapping design memories to integrated circ...