Ivor G. Barber

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip gettering
- Patent number 11,393,697
- Issue date Jul 19, 2022
- Advanced Micro Devices, Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip gettering
- Patent number 10,825,692
- Issue date Nov 3, 2020
- Advanced Micro Devices, Inc.
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing system for lid-less integrated circuit packages
- Patent number 10,527,670
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Gamal Refai-Ahmed
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for thermal interface material (TIM) bond lin...
- Patent number 10,529,645
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded chip combination
- Patent number 10,510,721
- Issue date Dec 17, 2019
- Advanced Micro Devices, Inc.
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with enhanced interconnects and method for fa...
- Patent number 10,319,606
- Issue date Jun 11, 2019
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for assembling and testing a multi-integrated...
- Patent number 10,096,502
- Issue date Oct 9, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having an enhanced lid
- Patent number 10,043,730
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package configuration and manufacturing method enabling the additio...
- Patent number 7,829,424
- Issue date Nov 9, 2010
- LSI Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package configuration and manufacturing method enabling the additio...
- Patent number 7,508,062
- Issue date Mar 24, 2009
- LSI Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package and method having wire-bonded intra-die...
- Patent number 7,173,328
- Issue date Feb 6, 2007
- LSI Logic Corporation
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via construction for structural support
- Patent number 6,943,446
- Issue date Sep 13, 2005
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal and mechanical attachment of a heatspreader to a flip-chip...
- Patent number 6,673,708
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal and mechanical attachment of a heatspreader to a flip-chip...
- Patent number 6,590,292
- Issue date Jul 8, 2003
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with minimized bond finger connections
- Patent number 5,895,968
- Issue date Apr 20, 1999
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of packaging integrated circuits
- Patent number 5,801,072
- Issue date Sep 1, 1998
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with minimized bond finger connections
- Patent number 5,741,726
- Issue date Apr 21, 1998
- LSI Logic Corporation
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of flip chip assembly
- Patent number 5,723,369
- Issue date Mar 3, 1998
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of packaging an integrated circuit
- Patent number 5,700,723
- Issue date Dec 23, 1997
- LSI Logic Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with minimized bond finger connections
- Patent number 5,604,161
- Issue date Feb 18, 1997
- LSI Logic Corporation
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with minimized bond finger connections
- Patent number 5,545,923
- Issue date Aug 13, 1996
- LSI Logic Corporation
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR CHIP GETTERING
- Publication number 20210050223
- Publication date Feb 18, 2021
- ADVANCED MICRO DEVICES, INC.
- RAHUL AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP GETTERING
- Publication number 20200203177
- Publication date Jun 25, 2020
- Rahul Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOLDED CHIP COMBINATION
- Publication number 20190051633
- Publication date Feb 14, 2019
- Milind S. Bhagavat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...
- Publication number 20180358280
- Publication date Dec 13, 2018
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING SYSTEM FOR LID-LESS INTEGRATED CIRCUIT PACKAGES
- Publication number 20180284187
- Publication date Oct 4, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED...
- Publication number 20180144963
- Publication date May 24, 2018
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID
- Publication number 20170092619
- Publication date Mar 30, 2017
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF
- Publication number 20140191403
- Publication date Jul 10, 2014
- LSI Corporation
- Ivor G. Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit System Monitor
- Publication number 20090285261
- Publication date Nov 19, 2009
- LSI Corporation
- Michael J. Casey
- G01 - MEASURING TESTING
Information Patent Application
PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITIO...
- Publication number 20080272863
- Publication date Nov 6, 2008
- LSI Logic Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Package configuration and manufacturing method enabling the additio...
- Publication number 20060202303
- Publication date Sep 14, 2006
- LSI Logic Corporation
- Leah Miller
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit package and method having wire-bonded intra-die...
- Publication number 20050224964
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Ivor Barber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via construction
- Publication number 20040089953
- Publication date May 13, 2004
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS

Ivor G. Barber

Person

Patents Grantslast 30 patents

Semiconductor chip gettering

Semiconductor chip gettering

Testing system for lid-less integrated circuit packages

Methods and apparatus for thermal interface material (TIM) bond lin...

Molded chip combination

Chip package assembly with enhanced interconnects and method for fa...

Method and apparatus for assembling and testing a multi-integrated...

Stacked silicon package assembly having an enhanced lid

Package configuration and manufacturing method enabling the additio...

Package configuration and manufacturing method enabling the additio...

Integrated circuit package and method having wire-bonded intra-die...

Via construction for structural support

Thermal and mechanical attachment of a heatspreader to a flip-chip...

Thermal and mechanical attachment of a heatspreader to a flip-chip...

Semiconductor device assembly with minimized bond finger connections

Method of packaging integrated circuits

Semiconductor device assembly with minimized bond finger connections

Method of flip chip assembly

Method of packaging an integrated circuit

Semiconductor device assembly with minimized bond finger connections

Semiconductor device assembly with minimized bond finger connections

Patents Applicationslast 30 patents

SEMICONDUCTOR CHIP GETTERING

SEMICONDUCTOR CHIP GETTERING

MOLDED CHIP COMBINATION

METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...

TESTING SYSTEM FOR LID-LESS INTEGRATED CIRCUIT PACKAGES

METHOD AND APPARATUS FOR ASSEMBLING AND TESTING A MULTI-INTEGRATED...

STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID

MULTI-DIE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF

Integrated Circuit System Monitor

PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITIO...

Package configuration and manufacturing method enabling the additio...

Integrated circuit package and method having wire-bonded intra-die...

Via construction