Patent Application
20140191403
This application is directed, in general, to semiconductor packages and, more specifically, to a multi-die semiconductor package and methods of manufacturing thereof.
A semiconductor package is a casing, typically made of plastic, glass or ceramic, that houses one or more integrated circuit (“IC”) dies and provides interconnections allowing circuitry associated with the IC die(s) to communicate signals with other circuitry outside of the semiconductor package.
Occasionally semiconductor packages are required to contain two instances of the same circuitry interconnected to cooperate with one another in some manner. Such packages may be assembled by bonding two instances of identical IC dies onto a common substrate, which supports the dies and provides the necessary interconnections, and then forming the casing around the substrate and dies. Assuming the two identical IC dies are placed side by side, the interconnections bridging like terminals in the dies extend, for example, from the left-hand side of the left die to the left-hand side of the right die, which typically means that the underlying interconnections extend underneath the left die. This arrangement continues to be proven and useful.
One aspect provides a multi-die semiconductor package. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first IC that substantially occupies an area of the first die, (3) a second die coupled to the substrate, the second die having a second set of terminals and bearing a second IC that substantially occupies an area of the second die, the first and second ICS being mirror-images of one another and (4) interconnects coupling corresponding terminals of the first and second sets together.
Another aspect provides a method of manufacturing a semiconductor package. In one embodiment, the method includes: (1) coupling a first die to a substrate, the first die having a first set of terminals located along a first edge and bearing a first IC that substantially occupies an area of the first die and (2) coupling a second die to the substrate, the second die having a second set of terminals and bearing a second IC that substantially occupies an area of the second die, the first and second ICs being mirror-images of one another, interconnects coupling corresponding terminals of the first and second sets together.
In another embodiment, the method includes: (1) creating an IC design, (2) creating a first layout of the design that has multiple layers, (3) creating a second layout of the design that is a mirror image of the first layout, corresponding ones of the multiple layers of the first and second layouts being mirror images of one another, (4) employing the first layout to fabricate a first die, (5) employing the second layout to fabricate a second die and (6) collocating the first and second dies in the semiconductor package.
Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
As stated above, the conventional arrangement described above (in which two identical IC dies are placed side by side and the interconnections bridging like terminals in the dies extend from the left-hand side of the left die to the left-hand side of the right die) continues to be proven and useful. However, it is realized herein that such arrangement has substantial limits.
Most notably, the demand for ever-higher performance from ICs has driven signal speeds to the point that the length of the interconnects required to span a side of one die to the corresponding side of the other die is too great; setup violations become more prevalent as speed-of-light limitations cause signals to arrive too late. It is realized that, for this reason, a fundamentally different approach is needed, and one that allows interconnections to be shorter and thus faster.
While stacking IC dies over one other has been contemplated to shorten interconnect length and reduce signal delays, they suffer problems of their own, including thermal problems. It is further realized that a fundamentally different approach is needed that does not involve stacking identical IC dies.
Accordingly, introduced herein are various embodiments of a semiconductor package containing two interconnected IC dies having identical circuitry designs. However, rather than the IC dies themselves being identical, they are mirror images of one another in that the entire pattern of circuitry laid out on one die is a mirror-image of the entire pattern of circuitry laid out on the other. Further, the entire pattern in each layer of circuitry laid out on one die is a mirror-image of its counterpart pattern in each corresponding layer laid out on the other die. One may properly regard one die as being left-handed and the other die as being right-handed. As a result, at least some of the interconnections spanning the dies are substantially shorter than they otherwise would be, and the costs of labor and material involved in designing and fabricating multi-die semiconductor packaging are reduced.
As will be understood, some embodiments of the novel semiconductor package may be manufactured by employing a software command to “flip” the entirety of each layer of a layout. Layouts are saved both before and after issuance of the flip command, resulting in mirror-image IC layouts, which can then be used to fabricate the mirror-image IC dies. Those skilled in the art understand that while the flip command is itself conventional, it has only been employed to flip particular functional blocks (sometimes called hard macros, modules or IP blocks) and never entire designs. Those skilled in the pertinent art understand that no motivation would exist to employ a flip command to flip an entire design absent the novel realizations and need for mirror-image IC dies described above, because a designer would instead begin the design process by laying out a design appropriate to the context in which the resulting IC die would be employed.
Using a pair of mirror-image IC dies instead of identical IC dies is also counterintuitive, because it necessarily increases the number of unique parts in the semiconductor design. Conventional wisdom dictates that numbers of unique parts should be kept as low as possible to reduce design, manufacturing and inventory storage costs. But it is realized that the time and effort spent in creating the mirror-image IC dies are negligible compared to the significant improvement a mirror-image IC die pair provides over an identical IC die pair.
It is realized that using ‘mirror-image’ IC die pair in a semiconductor package may significantly shorten the length of interconnects between the corresponding terminals of the paired IC dies. A ‘mirror image’ IC dies refers to an IC die having a spatial arrangement that corresponds to that of another IC die except that the right-to-left or East-to-West sense on one IC die corresponds to the left-to-right or West-to-East sense on the other. The ‘mirror-image’ IC die pair in the present disclosure would comprise a right-handed die and a left-handed die that are placed side-by-side on a common substrate with their edges having terminals for interconnects being adjacent to one another. As the corresponding terminals are closely situated to one another, one may shorten the lengths of interconnects and reduce latency and power consumption thereof.
As used throughout in the present disclosure, the term “IC die” or simply “die” refers to any monolithic electronic device or circuit that may be coupled to a substrate inside a semiconductor package. The term “IC” or “integrated circuit” refers to circuitry embedded in a silicon die.
Referring to
The first mirror-image IC die 120 has North 212 and South edges 214 extending along the length of the substrate 110 and has East 216 and West 218 edges extending along the width of the substrate 110. The first IC die 120 also has a set of terminals 230 located along the East edge 216 and at least one Integrated circuit (“IC”) 250 that substantially occupies an area of the first IC die 120. In various embodiments, the first IC die 120 includes further sets of terminals located along other edges thereof.
The second IC die 130 has North 222 and South edges 224 extending along the length of the substrate 110 and has East 226 and West 228 edges extending along the width of the substrate 110. The second IC die 130 also has a set of terminals 240 located along the West edge 228 and also has at least one IC 260 that substantially occupies an area of the second IC die 130. In various embodiments, the second IC die 130 includes further sets of terminals located along other edges thereof.
Still referring to
In another exemplary embodiment shown in
Turning now to
In steps 640, 650, first and second dies are fabricated employing the first and the second layouts, respectively. The steps 640, 650 may be carried out sequentially using two reticles as described in
Turning to
In step 720, a second die is coupled to the substrate. The second die has a second set of terminals and a second IC that substantially occupies an area of the second die. The first and second ICs are mirror-images of one another and collocated in a common substrate such that the first edge of the first die and the second edge of the second die are substantially parallel and side-by-side with one another, resulting in the interconnects that couple the corresponding terminals in the first and second edges being substantially parallel. In the illustrated embodiment, the interconnects lie outside of the areas of the first and second ICs. In certain embodiments, the second die has further sets of terminals located along other edges of the second die. It is also understood that the semiconductor package may be in various formats including, but not limited to, a multi-chip module format, 2.5D format and a SoC format. The method ends in an end step 725.
Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
