Jae Hun Ku

Person

Signapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming insulating layer in notc...
- Patent number 9,837,336
- Issue date Dec 5, 2017
- STATS ChipPAC, Pte. Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming UBM structure on back su...
- Patent number 9,601,462
- Issue date Mar 21, 2017
- STATS ChipPAC Pte. Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming TSV interposer with semi...
- Patent number 9,224,647
- Issue date Dec 29, 2015
- STATS ChipPAC, Ltd.
- Jun Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of making TSV interconnect structur...
- Patent number 9,054,083
- Issue date Jun 9, 2015
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming UBM structure on back su...
- Patent number 8,809,191
- Issue date Aug 19, 2014
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming insulating layer in notc...
- Patent number 8,742,591
- Issue date Jun 3, 2014
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having an interconnect structure with TSV usin...
- Patent number 8,659,162
- Issue date Feb 25, 2014
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe and semiconductor package made using the leadframe
- Patent number 8,410,585
- Issue date Apr 2, 2013
- Amkor Technology, Inc.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with transparent encapsulation...
- Patent number 8,399,306
- Issue date Mar 19, 2013
- Stats Chippac Ltd.
- JunMo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming an interconnect structur...
- Patent number 8,067,308
- Issue date Nov 29, 2011
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Large die package structures and fabrication method therefor
- Patent number 8,035,204
- Issue date Oct 11, 2011
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Large die package structures and fabrication method therefor
- Patent number 7,700,404
- Issue date Apr 20, 2010
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with leadframe locked encapsulation and...
- Patent number 7,413,933
- Issue date Aug 19, 2008
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual row leadframe and fabrication method
- Patent number 7,339,258
- Issue date Mar 4, 2008
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with leadframe locked encapsulation and...
- Patent number 7,217,599
- Issue date May 15, 2007
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Large die package structures and fabrication method therefor
- Patent number 7,129,569
- Issue date Oct 31, 2006
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual row leadframe and fabrication method
- Patent number 7,060,536
- Issue date Jun 13, 2006
- ST Assembly Test Services Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe and semiconductor package made using the leadframe
- Patent number 7,042,068
- Issue date May 9, 2006
- Amkor Technology, Inc.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package
- Patent number 6,953,988
- Issue date Oct 11, 2005
- Amkor Technology, Inc.
- Seong Min Seo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package including stacked chips with aligned input/ou...
- Patent number 6,759,737
- Issue date Jul 6, 2004
- Amkor Technology, Inc.
- Seong Min Seo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method of Forming UBM Structure on Back Su...
- Publication number 20140264851
- Publication date Sep 18, 2014
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Insulating Layer in Notc...
- Publication number 20140225279
- Publication date Aug 14, 2014
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Having an Interconnect Structure with TSV Usin...
- Publication number 20140110861
- Publication date Apr 24, 2014
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Insulating Layer in Notc...
- Publication number 20130161824
- Publication date Jun 27, 2013
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming UBM Structure on Back Su...
- Publication number 20130147036
- Publication date Jun 13, 2013
- STATS ChipPAC, Ltd.
- Won Kyoung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION...
- Publication number 20120241927
- Publication date Sep 27, 2012
- JunMo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming TSV Interposer With Semi...
- Publication number 20120074585
- Publication date Mar 29, 2012
- STATS ChipPAC, Ltd.
- Jun Mo Koo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Having an Interconnect Structure with TSV Usin...
- Publication number 20120013004
- Publication date Jan 19, 2012
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming an Interconnect Structur...
- Publication number 20100308443
- Publication date Dec 9, 2010
- STATS ChipPAC, Ltd.
- Nathapong Suthiwongsunthorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
- Publication number 20100140766
- Publication date Jun 10, 2010
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND...
- Publication number 20070190694
- Publication date Aug 16, 2007
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
- Publication number 20070018290
- Publication date Jan 25, 2007
- STATS ChipPAC Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL ROW LEADFRAME AND FABRICATION METHOD
- Publication number 20060186515
- Publication date Aug 24, 2006
- STATS ChipPAC Ltd.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leadframe and semiconductor package made using the leadframe
- Publication number 20060151858
- Publication date Jul 13, 2006
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual row leadframe and fabrication method
- Publication number 20050260787
- Publication date Nov 24, 2005
- ST ASSEMBLY TEST SERVICES
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Large die package structures and fabrication method therefor
- Publication number 20050253230
- Publication date Nov 17, 2005
- ST ASSEMBLY TEST SERVICES LTD.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit package with leadframe locked encapsulation and...
- Publication number 20040253763
- Publication date Dec 16, 2004
- ST ASSEMBLY TEST SERVICES LTD.
- Jeffrey D. Punzalan
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming insulating layer in notc...

Semiconductor device and method of forming UBM structure on back su...

Semiconductor device and method of forming TSV interposer with semi...

Semiconductor device and method of making TSV interconnect structur...

Semiconductor device and method of forming UBM structure on back su...

Semiconductor device and method of forming insulating layer in notc...

Semiconductor device having an interconnect structure with TSV usin...

Leadframe and semiconductor package made using the leadframe

Integrated circuit packaging system with transparent encapsulation...

Semiconductor device and method of forming an interconnect structur...

Large die package structures and fabrication method therefor

Large die package structures and fabrication method therefor

Integrated circuit package with leadframe locked encapsulation and...

Dual row leadframe and fabrication method

Integrated circuit package with leadframe locked encapsulation and...

Large die package structures and fabrication method therefor

Dual row leadframe and fabrication method

Leadframe and semiconductor package made using the leadframe

Semiconductor package

Semiconductor package including stacked chips with aligned input/ou...

Patents Applicationslast 30 patents

Semiconductor Device and Method of Forming UBM Structure on Back Su...

Semiconductor Device and Method of Forming Insulating Layer in Notc...

Semiconductor Device Having an Interconnect Structure with TSV Usin...

Semiconductor Device and Method of Forming Insulating Layer in Notc...

Semiconductor Device and Method of Forming UBM Structure on Back Su...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION...

Semiconductor Device and Method of Forming TSV Interposer With Semi...

Semiconductor Device Having an Interconnect Structure with TSV Usin...

Semiconductor Device and Method of Forming an Interconnect Structur...

LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR

INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND...

LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR

DUAL ROW LEADFRAME AND FABRICATION METHOD

Leadframe and semiconductor package made using the leadframe

Dual row leadframe and fabrication method

Large die package structures and fabrication method therefor

Integrated circuit package with leadframe locked encapsulation and...